2.1.6

ASP: Transfers Should be Buffered in Internal Memory

2.1.7

ASP: Initialization Procedure When External Device is Frame-Sync Master

2.1.8

NAND Layout Assumed by RBL for Big Block NAND Does Not Match NAND Manufacturers'

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Silicon Revision 1.1 Usage Notes and Known Design Exceptions to Functional Specifications

In DM335 Silicon Revision 1.1, Audio Serial Port (ASP) transfers may need to originate and complete from

on-chip buffers in ARM Internal RAM (TCM). This is due to the fact that there is no tolerance for audio

data dropouts that may occur due to the delays in DDR2/mDDR accesses from other masters and from

unavoidable DDR2/mDDR refresh cycles even if the Q0/TC0 is dedicated to transfers from off-chip

memories. On-chip buffers might be needed to ensure immunity from DDR2/mDDR latencies.

DDR2/mDDR latencies are system-dependent, varying between applications, and are impacted by the

amount and type of data traffic to DDR2/mDDR memories. Once completed, the data can be shuttled

between the internal buffer and the DDR2/mDDR memory by using EDMA Q1/TC1.

If using on-chip buffers for ASP transfers, also see the following advisories:

• 1.1.2 Concurrent Access to ARM Internal Memory May Result in Access Errors

On DM335 Silicon Revision 1.1, if the ASP transmitter expects a frame sync from an external device, care

must be taken to ensure that the proper action is employed. After the transmitter comes out of reset

(XRST = 1), it waits for a frame sync from the external device. If the first frame sync arrives very shortly

after the transmitter is enabled, the CPU or EDMA controller may not have a chance to service the ASP

data transmit register (DXR). In this case, the transmitter shifts out the default data in the transmit shift

register (XSR) instead of the desired value, which has not yet arrived in the DXR. This causes problems in

some applications such that the first data element in the frame is invalid. The data stream appears

element-shifted (the first data word may appear in the second channel instead of the first).

To ensure proper operation when the external device is the frame master, you must make sure that the

DXR is already serviced with the first word when a frame sync occurs. To do so, you can keep the

transmitter in reset until the first frame sync is detected. The software is set up such that it will only take

the transmitter out of reset (XRST = 1) promptly after detecting the first frame sync. This ensures that the

transmitter does not begin data transfers at the data pin during the first frame-sync period. This also

provides almost an entire frame period for the DM335 device to service the DXR with the first word before

the second frame sync occurs. The transmitter only begins data transfers upon receiving the second

frame sync. At this point, the DXR is already serviced with the first word.

The ASP transmitter and receiver on the DM335 device are capable of generating an interrupt upon the

detection of frame synchronization. However, on the DM335 device, the receiver and/or transmitter must

be out of reset to enable this feature. Therefore, instead of directly using the ASP interrupt to detect the

first frame sync, on the DM335 device you can use the GPIO peripheral. This can be achieved by

connecting the frame-sync signal to a GPIO pin. The software can either poll the GPIO pin to detect the

first frame sync or program the GPIO peripheral to generate an interrupt to the CPU upon detecting the

first frame-sync edge. For more information on the GPIO peripheral, see the TMS320DM335 DMSoC

General-Purpose Input/Output (GPIO) User's Guide (SPRUFY8). For details on the initialization sequence

when the external device is the frame-sync master, see the TMS320DM335 DMSoC Audio Serial Port

(ASP) User's Guide (SPRUFZ3).

Recommendations

Typically NAND manufactures place Bad Block information in the spare bytes area. The RBL assumes a

data layout as below:

512 bytes Data

16 bytes ECC Data

512 bytes Data

16 bytes ECC Data

512 bytes Data

16 bytes ECC Data

512 bytes Data

16 bytes ECC Data

SPRZ287A – July 2008 – Revised October 2008

TMS320DM335 Digital Media System-on-Chip (DMSoC)

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Silicon Revision 1.1

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