SPIx_CLK

SPIx_SIMO

(a)WriteSPIDA T1

=0x10001245

(CSHOLD=1)

(b)WriteSPIDA T1

=0x00005678

(CSHOLD=0)

(a)

(b)

SPI_ENx

SPIx_CLK

SPIx_SIMO

(a)WriteSPIDA T1

=0x10001245

(CSHOLD=1)

(b)WriteSPIDA T1

=0x00005678

(CSHOLD=0)

(a)

(b)

SPI_ENx

Advisory 1.1.8 — SPI Master Mode: Extra Step Required to Use CSHOLD

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Advisory 1.1.8

SPI Master Mode: Extra Step Required to Use CSHOLD

Revision(s) Affected

1.1

Details

The SPI module chip-select hold (CSHOLD) feature allows the device to instruct the SPI

to keep the chip-select pin asserted between transfers. This feature applies in master

mode and is enabled by writing a '1' to SPIDAT1.CSHOLD (bit 28).

When data is written to the SPIDAT1 register with the CSHOLD bit set to '1', the master

is supposed to keep the SPI_ENx pin asserted after the transfer completes. When data

is written to the SPIDAT1 register with CSHOLD set to '0', the master is supposed to

de-assert the SPI_ENx pin after the transfer completes.

For example, assume that the device needs to send two 16-bit words (0x1234 and

0x5678) to an SPI slave that requires its chip select to remain asserted between the

transfers. This is a common requirement when communicating with SPI memory devices.

According to the SPI specification, the following sequence should produce the expected

result as illustrated in Figure 2:

• Write 0x10001234 to SPIDAT1 for transmission of 0X1234 (CSHOLD = 1)

• Write 0x00005678 to SPIDAT1 for transmission of 0x5678 (CSHOLD = 0)

Figure 2. Expected CSHOLD Behavior

Instead, what actually occurs is that SPI_ENx is momentarily de-asserted at the

beginning of the second write, as illustrated in Figure 3.

Figure 3. Actual CSHOLD Behavior–32-Bit Writes to SPIDAT1

18

TMS320DM335 Digital Media System-on-Chip (DMSoC)

SPRZ287A – July 2008 – Revised October 2008

Silicon Revision 1.1

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