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LTC1871-7

18717fc

APPLICATIONS INFORMATION

7. Minimize the capacitance between the SENSE pin trace

and any high frequency switching nodes. The LTC1871-7

contains an internal leading edge blanking time of ap-

proximately 180ns, which should be adequate for most

applications.

8. For optimum load regulation and true remote sens-

ing, the top of the output resistor divider should connect

independently to the top of the output capacitor (Kelvin

connection), staying away from any high dV/dt traces.

Place the divider resistors near the LTC1871-7 in order

to keep the high impedance FB node short.

Figure 18. LTC1871-7 Boost Converter Suggested Layout

Figure 19. LTC1871-7 Boost Converter Layout Diagram

LTC1871-7

VIN

1871 F18

VOUT

SWITCH NODE IS ALSO

THE HEAT SPREADER

FOR L1, M1, D1

CIN

COUT

CVCC

PSEUDO-KELVIN

SIGNAL GROUND

CONNECTION

TRUE REMOTE

OUTPUT SENSING

VIAS TO GROUND

PLANE

PIN 1

COUT

JUMPER

RUN

ITH

FREQ

MODE/

SYNC

SENSE

VIN

INTVCC

GATE

GND

LTC1871-7

CVCC

PSEUDO-KELVIN

GROUND CONNECTION

CIN

VIN

GND

18717 F19

VOUT

SWITCH

NODE

COUT

BOLD LINES INDICATE HIGH CURRENT PATHS

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