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PCI1221 Datasheet(PDF) 50 Page - Texas Instruments |
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PCI1221 Datasheet(HTML) 50 Page - Texas Instruments |
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50 / 123 page  PCI1221 GHK/PDV PC CARD CONTROLLERS SCPS042 – JULY 1998 50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CardBus socket registers/ExCA base-address register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CardBus socket/ExCA base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CardBus socket/ExCA base address Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: CardBus socket/ExCA base address Type: Read only, read/write Offset: 10h Default: 0000 0000h Description: The CardBus socket registers/ExCA base-address register is programmed with a base address referencing the CardBus socket registers and the memory-mapped ExCA register set. Bits 31-12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4K-byte boundary. Bits 11-0 are read only, returning 0s when read. When software writes all 1s to this register, the value readback is FFFF F000h, indicating that at least 4K-bytes of memory address space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers begin at offset 800h. Since this register is not shared by functions 0 and 1, mapping of each socket control is performed separately. capability pointer register Bit 7 6 5 4 3 2 1 0 Name Capability pointer Type R R R R R R R R Default 1 0 1 0 0 0 0 0 Register: Capability pointer Type: Read only Offset: 14h Default: A0h Description: The capability pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. Each socket has its own capability pointer register. This register is read only and returns A0h when read. |
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