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PCI1221 Datasheet(PDF) 59 Page - Texas Instruments

Part # PCI1221
Description  PC CARD CONTROLLERS
PDF  123 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PCI1221 Datasheet(HTML) 59 Page - Texas Instruments

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PCI1221 GHK/PDV
PC CARD CONTROLLERS
SCPS042 – JULY 1998
59
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PC Card 16-bit I/F legacy-mode base address register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
PC Card 16-bit I/F legacy-mode base address
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
PC Card 16-bit I/F legacy-mode base address
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Register:
PC Card 16-bit I/F legacy-mode base address
Type:
Read only, read/write (see individual bit descriptions)
Offset:
44h (functions 0, 1)
Default:
0000 0001h
Description: The PCI1221 supports the index/data scheme of accessing the ExCA registers, which is
mapped by this register. An address written to this register is the address for the index register
and the address + 1 is the data address. Using this access method, applications requiring
index/data ExCA access can be supported. The base address can be mapped anywhere in
32-bit I/O space on a word boundary; hence, bit 0 is read only, returning 1 when read. As
specified in the
PCI to PCMCIA CardBus Bridge Register Description (Yenta), this register is
shared by functions 0 and 1. Refer to
ExCA compatibility registers on page 80 for register
offsets.
system control register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
System control
Type
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
System control
Type
R/W
R/W
R
R
R
R
R
R
R
R/W
R/W
R/W
R
R
R/W
R/W
Default
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
Register:
System control
Type:
Read only, read/write (see individual bit descriptions)
Offset:
80h (functions 0, 1)
Default:
0040 9060h
Description: System-level initializations are performed through programming this doubleword register.
Some of the bits are global and should be written only through function 0. See Table 21 for a
complete description of the register contents.



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