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PCI1221 Datasheet(PDF) 55 Page - Texas Instruments |
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PCI1221 Datasheet(HTML) 55 Page - Texas Instruments |
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55 / 123 page  PCI1221 GHK/PDV PC CARD CONTROLLERS SCPS042 – JULY 1998 55 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 I/O limit registers 0, 1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name I/O limit registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I/O limit registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: I/O limit registers 0, 1 Type: Read only, read/write Offset: 30h, 38h Default: 0000 0000h Description: The I/O limit registers indicate the upper address of a PCI I/O address range. These registers are used by the PCI1221 to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64K-byte page, and the upper 16 bits are a page register that locates this 64K-byte page in 32-bit PCI I/O address space. Bits 15-2 are read/write and allow the I/O limit address to be located anywhere in the 64K-byte page (indicated by bits 31-16 of the appropriate I/O base) on doubleword boundaries. Bits 31-16 are read only and always return 0s when read. The page is set in the I/O base register. Bits 1-0 are read only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. Write transactions to read-only bits have no effect. The PCI1221 assumes that the lower two bits of the limit address are 1s. NOTE: The I/O base or the I/O limit register must be nonzero to enable an I/O transaction. interrupt line register Bit 7 6 5 4 3 2 1 0 Name Interrupt line Type R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 Register: Interrupt line Type: Read/write Offset: 3Ch Default: FFh Description: The interrupt line register is read/write and is used to communicate interrupt line routing information. Each PCI1221 function has an interrupt line register. |
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