PCI1221 datasheet(57/123 Pages) TI

57 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

bridge control register

Bit

Name

Bridge control

Type

R/W

Default

Bridge control

Type:

Read only, read/write (see individual bit descriptions)

Offset:

3Eh (functions 0, 1)

Default:

0340h

Description: The bridge control register provides control over various PCI1221 bridging functions. Some

bits in this register are global and should be accessed only through function 0. See Table 20

for a complete description of the register contents.

Table 20. Bridge Control Register

BIT

SIGNAL

TYPE

FUNCTION

15–11

RSVD

Reserved. Bits 15–11 return 0s when read.

POSTEN

R/W

Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables

posting of write data on burst cycles. Operating with write posting disabled inhibits performance on burst

cycles. Note that bursted write data can be posted, but various write transactions may not. Bit 10 is socket

dependent and is not shared between functions 0 and 1.

PREFETCH1

R/W

Memory window 1 type. Bit 9 specifies whether or not memory window 1 is prefetchable. This bit is socket

dependent. Bit 9 is encoded as:

0 = Memory window 1 is nonprefetchable.

1 = Memory window 1 is prefetchable (default).

PREFETCH0

R/W

Memory window 0 type. Bit 8 specifies whether or not memory window 0 is prefetchable. This bit is

encoded as:

0 = Memory window 0 is nonprefetchable.

1 = Memory window 0 is prefetchable (default).

INTR

R/W

PCI interrupt – IREQ routing enable. Bit 7 is used to select whether PC Card functional interrupts are

routed to PCI interrupts or the IRQ specified in the ExCA registers.

0 = Functional interrupts routed to PCI interrupts (default)

1 = Functional interrupts routed by ExCAs

CRST

R/W

CardBus reset. When bit 6 is set, CRST is asserted on the CardBus interface. CRST can also be

asserted by passing a PRST assertion to CardBus.

0 = CRST deasserted

1 = CRST asserted (default)

5†

MABTMODE

R/W

Master abort mode. Bit 5 controls how the PCI1221 responds to a master abort when the PCI1221 is

an initiator on the CardBus interface. This bit is common between each socket.

0 = Master aborts not reported (default)

1 = Signal target abort on PCI and SERR (if enabled)

RSVD

Reserved. Bit 4 returns 0 when read.

VGAEN

R/W

VGA enable. Bit 3 affects how the PCI1221 responds to VGA addresses. When this bit is set, accesses

to VGA addresses are forwarded.

ISAEN

R/W

ISA mode enable. Bit 2 affects how the PCI1221 passes I/O cycles within the 64K-byte ISA range. This

bit is not common between sockets. When this bit is set, the PCI1221 does not forward the last 768 bytes

of each 1K I/O range to CardBus.

1†

CSERREN

R/W

CSERR enable. Bit 1 controls the response of the PCI1221 to CSERR signals on the CardBus bus. This

bit is common between the two sockets.

0 = CSERR is not forwarded to PCI SERR.

1 = CSERR is forwarded to PCI SERR.

0†

CPERREN

CardBus parity error response enable. Bit 0 controls the response of the PCI1221 to CardBus parity

errors. This bit is common between the two sockets.

0 = CardBus parity errors are ignored.

1 = CardBus parity errors are reported using CPERR.

† These bits are global and should be accessed only through function 0.

PCI1221 Datasheet(PDF) 57 Page - Texas Instruments

PCI1221 Datasheet(HTML) 57 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL