PCI1221 datasheet(60/123 Pages) TI

60 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Table 21. System Control Register

BIT

SIGNAL

TYPE

FUNCTION

31–30†

SER_STEP

R/W

Serialized PCI interrupt routing step. Bits 31–30 are used to configure the serialized PCI interrupt

stream signaling, and accomplish an even distribution of interrupts signaled on the four PCI interrupt

slots. Bits 31–30 are global to all PCI1221 functions.

00 = INTA/INTB signal in INTA/INTB IRQSER slots

01 = INTA/INTB signal in INTB/INTC IRQSER slots

10 = INTA/INTB signal in INTC/INTD IRQSER slots

11 = INTA/INTB signal in INTD/INTA IRQSER slots

29†

INTRTIE

R/W

Tie internal PCI interrupts. When this bit is set, the INTA and INTB signals are tied together internally

and are signaled as INTA. INTA can then be shifted by using the SER_STEP bits. This bit is global to

all PCI1221 functions.

When configuring the PCI1221 functions to share PCI interrupts, multifunction terminal MFUNC3 must

be configured as IRQSER prior to setting the INTRTIE bit.

RSVD

Reserved. Bit 28 is read only and returns 0 when read.

27†

P2CCLK

R/W

P2C power switch clock. The PCI1221 defaults CLOCK as an input clock to control the serial interface

and the internal state machine. Bit 27 can be set to enable the PCI1221 to generate and drive the

CLOCK from the PCI clock. When in a SUSPEND state, however, CLOCK must be input to the

PCI1221 to successfully power down sockets after card removal without indicating to the system the

removal event.

0 = CLOCK provided externally, input to PCI1221 (default)

1 = CLOCK generated by PCI clock and driven by PCI1221

26†

SMIROUTE

R/W

SMI interrupt routing. Bit 26 is shared between functions 0 and 1, and selects whether IRQ2 or CSC

is signaled when a write occurs to power a PC Card socket.

0 = PC Card power change interrupts routed to IRQ2 (default)

1 = A CSC interrupt is generated on PC Card power changes.

SMISTATUS

R/W

SMI interrupt status. This socket-dependent bit is set when a write occurs to set the socket power, and

the SMIENB bit is set. Writing a 1 to bit 25 clears the status.

0= SMI interrupt signaled (default)

1 = SMI interrupt not signaled

24†

SMIENB

R/W

SMI interrupt mode enable. When bit 24 is set, the SMI interrupt signaling is enabled and generates

an interrupt when a write to the socket power control occurs. This bit is shared and defaults to 0

(disabled).

RSVD

Reserved. This bit is read only and returns 0 when read.

CBRSVD

R/W

CardBus reserved terminals signaling. When bit 22 is set, the RSVD CardBus terminals are driven low

when a CardBus card is inserted. When this bit is low (as default), these signals are 3-stated.

0 = 3-state CardBus RSVD

1 = Drive Cardbus RSVD low (default)

VCCPROT

R/W

VCC protection enable. Bit 21 is socket dependent.

0 = VCC protection enabled for 16-bit cards (default)

1 = VCC protection disabled for 16-bit cards

REDUCEZV

R/W

Reduced Zoom Video Enable. When this bit is enabled, A25–22 of the card interface for PC Card 16

cards is placed in the high impedance state. This bit should not be set for normal ZV operation. This

bit is encoded as:

0 = Reduced zoom video disabled (default)

1 = Reduced zoom video enabled

19-16

RSVD

Reserved. These bits are reserved and return 0’s when read.

† These bits are global and should be accessed only through function 0.

PCI1221 Datasheet(PDF) 60 Page - Texas Instruments

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