PCI1221 datasheet(66/123 Pages) TI

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PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

card control register

Bit

Name

Card control

Type

R/W

R/C

Default

Card control

Type:

Read only, read/write, read/clear (see individual bit descriptions)

Offset:

91h

Default:

00h

Description: The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through

this register, and the enable bit is shared between functions 0 and 1. See Table 24 for a

complete description of the register contents.

Table 24. Card Control Register

BIT

SIGNAL

TYPE

FUNCTION

7†

RIENB

R/W

Ring indicate output enable.

0 = Disables any routing of RI_OUT signal (default).

1 = Enables RI_OUT signal for routing to the RI_OUT/PME terminal when

RIMUX is set to 0, and for routing to MFUNC2/4.

ZVENABLE

R/W

Compatibility ZV mode enable. When set, the corresponding PC Card Socket interface ZV terminals

enter a high-impedance state. This bit defaults to 0.

PORT_SEL

R/W

Port Select. This bit controls the priority for the ZVSEL0 and ZVSEL1 signaling if ZVENABLE is set in

both functions.

0 = Socket 0 takes priority, as signaled through ZVSEL0, when both sockets are in ZV mode.

1 = Socket 1 takes priority, as signaled through ZVSEL1, when both sockets are in ZV mode.

4–3

RSVD

Reserved. Bits 4–3 are read only and default to 0.

AUD2MUX

R/W

CardBus Audio-to-IRQMUX. When set, the CAUDIO CardBus signal is routed to the corresponding

multifunction terminal which may be configured for CAUDPWM. When both socket 0 and 1 functions

have AUD2MUX set, socket 0 takes precedence.

SPKROUTEN

R/W

Speaker out enable. When bit 1 is set, SPKR on the PC Card is enabled and is routed to SPKROUT. The

SPKR signal from socket 0 is exclusive ORed with the SPKR signal from socket 1 and sent to SPKROUT.

The SPKROUT terminal drives data only when either functions SPKROUTEN bit is set. This bit is

encoded as:

0 = SPKR to SPKROUT not enabled

1 = SPKR to SPKROUT enabled

IFG

R/C

Interrupt flag. Bit 0 is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. Bit 0 is set when

a functional interrupt is signaled from a PC Card interface and is socket dependent (i.e., not global). Write

back a 1 to clear this bit.

0 = No PC Card functional interrupt detected (default).

1 = PC Card functional interrupt detected.

† This bit is global and should be accessed only through function 0.

PCI1221 Datasheet(PDF) 66 Page - Texas Instruments

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