PCI1221 datasheet(61/123 Pages) TI

61 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Table 21. System Control Register (Continued)

BIT

SIGNAL

TYPE

FUNCTION

15†

MRBURSTDN

R/W

Memory read burst enable downstream. When bit 15 is set, memory read transactions are allowed to

burst downstream.

0 = Downstream memory read burst is disabled.

1 = Downstream memory read burst is enabled (default).

14†

MRBURSTUP

R/W

Memory read burst enable upstream. When bit 14 is set, the PCI1221 allows memory read transactions

to burst upstream.

0 = Upstream memory read burst is disabled (default).

1 = Upstream memory read burst is enabled.

SOCACTIVE

Socket activity status. When set, bit 13 indicates access has been performed to or from a PC card and

is cleared upon read of this status bit. This bit is socket dependent.

0 = No socket activity (default)

1 = Socket activity

RSVD

Reserved. Bit 12 is read only and returns 1 when read.

11†

PWRSTREAM

Power stream in progress status bit. When set, bit 11 indicates that a power stream to the power switch

is in progress and a powering change has been requested. This bit is cleared when the power stream

is complete.

0 = Power stream is complete and delay has expired.

1 = Power stream is in progress.

10†

DELAYUP

Power-up delay in progress status. When set, bit 9 indicates that a power-up stream has been sent

to the power switch and proper power may not yet be stable. This bit is cleared when the power-up

delay has expired.

9†

DELAYDOWN

Power-down delay in progress status. When set, bit 10 indicates that a power-down stream has been

sent to the power switch and proper power may not yet be stable. This bit is cleared when the

power-down delay has expired.

INTERROGATE

Interrogation in progress. When set, bit 8 indicates an interrogation is in progress and clears when

interrogation completes. This bit is socket dependent.

0 = Interrogation not in progress (default)

1 = Interrogation in progress

RSVD

Reserved. Bit 7 is read only and returns 0 when read.

PWRSAVINGS

R/W

Power savings mode enable. When this bit is set, if a CB card is inserted, idle, and without a CB clock,

the applicable CB state machine will not be clocked.

5†

SUBSYSRW

R/W

Subsystem ID (SSID), subsystem vendor ID (SSVID), ExCA ID, and revision register read/write

enable. Bit 5 is shared by functions 0 and 1.

0 = SSID, SSVID, ExCA ID, and revision register are read/write.

1 = SSID, SSVID, ExCA ID, and revision register are read only (default).

4†

CB_DPAR

R/W

CardBus data parity SERR signaling enable

0 = CardBus data parity not signaled on PCI SERR

1 = CardBus data parity signaled on PCI SERR

3-2

RSVD

Reserved. This bit is read only and returns 0 when read.

1†

KEEPCLK

R/W

Keep clock. This bit works with PCI and CB CLKRUN protocols.

0 = Allows normal functioning of both CLKRUN protocols.(default)

1 = Does not allow CB clock or PCI clock to be stopped using the CLKRUN protocols.

RIMUX

R/W

RI_OUT/PME multiplex enable.

0 = RI_OUT and PME are both routed to the RI_OUT/PME terminal. If both are enabled

at the same time, RI_OUT has precedence over PME.

1 = Only PME is routed to the RI_OUT/PME terminal.

† These bits are global and should be accessed only through function 0.

PCI1221 Datasheet(PDF) 61 Page - Texas Instruments

PCI1221 Datasheet(HTML) 61 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL