TLC320AC02IPM datasheet(47/84 Pages) TI

47 / 84 page

3–8

3.6

Timing Requirements and Specifications in Master Mode

3.6.1

Recommended Input Timing Requirements for Master Mode, VDD = 5 V

MIN

NOM

MAX

UNIT

tr(MCLK)

Master clock rise time

tf(MCLK)

Master clock fall time

Master clock duty cycle

40%

60%

tw(RESET)

RESET pulse duration

1 MCLK

tsu(DIN)

DIN setup time before SCLK low (see Figure 4–2)

th(DIN)

DIN hold time after SCLK low (see Figure 4–2)

3.6.2

Operating Characteristics Over Recommended Range of Operating Free-Air

Temperature, VDD = 5 V (Unless Otherwise Noted) (see Note 23)

PARAMETER

MIN

TYP†

MAX

UNIT

tf(SCLK)

Shift clock fall time (see Figure 4–2)

tr(SCLK)

Shift clock rise time (see Figure 4–2)

Shift clock duty cycle

45%

55%

td(CH-FL)

Delay time from SCLK high to FSD low

(see Figures 4–2 and 4–4 and Note 24)

td(CH-FH)

Delay time from SCLK high to FS high (see Figure 4–2)

td(CH-DOUT)

Delay time from SCLK high to DOUT valid

(see Figures 4–2 and 4–7)

td(CH-DOUTZ)

Delay time from SCLK

↑ to DOUT in high-impedance state

(see Figure 4–8)

td(ML-EL)

Delay time from MCLK low to EOC low (see Figure 4–9)

td(ML-EH)

Delay time from MCLK low to EOC high (see Figure 4–9)

tf(EL)

EOC fall time (see Figure 4–9)

tr(EH)

EOC rise time (see Figure 4–9)

td(MH-CH)

Delay time from MCLK high to SCLK high

td(MH-CL)

Delay time from MCLK high to SCLK low

† All typical values are at VDD = 5 V and TA = 25°C.

NOTES: 23. All timing specifications are valid with CL = 20 pF.

24. FSD occurs 1/2 shift-clock cycle ahead of FS when the device is operating in the master mode.

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