TMS320UC5402 datasheet(33/63 Pages) TI

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TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

divide-by-two clock option (PLL disabled)

The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two to generate

the internal machine cycle. The selection of the clock mode is described in the clock generator section.

When an external clock source is used, the external frequency injected must conform to specifications listed

in the timing requirements table.

NOTE: If an external clock source is used, the CLKIN signal level should not exceed 1.98 V.

switching characteristics over recommended operating conditions [H = 0.5tc(CO)]† (see Figure 9,

Figure 10, and the recommended operating conditions table)

PARAMETER

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

12.50‡

2tc(CI)

†

td(CIH-CO)

Delay time, X2/CLKIN high to CLKOUT high/low

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

H–2

H–1

tw(COH)

Pulse duration, CLKOUT high

H–2

H–1

† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

‡ It is recommended that the PLL clocking option be used for maximum frequency operation.

timing requirements (see Figure 10)

MIN

MAX

UNIT

tc(CI)

Cycle time, X2/CLKIN

6.25

†

tf(CI)

Fall time, X2/CLKIN

tr(CI)

Rise time, X2/CLKIN

† This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

tr(CO)

tf(CO)

CLKOUT

X2/CLKIN

tw(COL)

td(CIH-CO)

tf(CI)

tr(CI)

tw(COH)

tc(CI)

tc(CO)

Figure 10. External Divide-by-Two Clock Timing

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