TMS320UC5402 datasheet(20/63 Pages) TI

20 / 63 page

TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

DMA controller

The ’UC5402 direct memory access (DMA) controller transfers data between points in the memory map without

intervention by the CPU. The DMA controller allows movements of data to and from internal program/data

memory or internal peripherals (such as the McBSPs) to occur in the background of CPU operation. The DMA

has six independent programmable channels, allowing six different contexts for DMA operation.

features

The DMA has the following features:

D The DMA operates independently of the CPU.

D The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.

D The DMA has higher priority than the CPU for internal accesses.

D Each channel has independently programmable priorities.

D Each channel’s source and destination address registers can have configurable indexes through memory

on each read and write transfer, respectively. The address may remain constant, be postincremented,

postdecremented, or be adjusted by a programmable value.

D Each read or write transfer may be initialized by selected events.

D Upon completion of a half-block or an entire-block transfer, each DMA channel may send an interrupt to the

CPU.

D The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words).

DMA memory map

The DMA memory map allows DMA transfers to be unaffected by the status of the MP/MC, DROM, and OVLY

bits. The DMAmemory map is identical to that of the HPI-8 controller shown in Figure 6.

DMA priority level

Each DMA channel can be independently assigned high priority or low priority relative to each other. Multiple

DMA channels that are assigned to the same priority level are handled in a round-robin manner.

DMA source/destination address modification

The DMA provides flexible address-indexing modes for easy implementation of data management schemes

such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and

can be postincremented, postdecremented, or postincremented with a specified index offset.

TMS320UC5402 Datasheet(PDF) 20 Page - Texas Instruments