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TMS320UC5402 Datasheet(PDF) 31 Page - Texas Instruments |
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TMS320UC5402 Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 63 page ![]() TMS320UC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS096A – APRIL 1999 – REVISED DECEMBER 1999 31 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics over recommended operating case temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High-level output voltage IOH = MAX DVDD – 0.3 V Lll t t DVDD = 1 71 to 1 89 V IOL = MAX CLKOUT 0.40 VOL Low-level output voltage DVDD = 1.71 to 1.89 V IOL = MAX All other outputs 0.35 V OL voltage DVDD = 1.9 to 3.6 V IOL = MAX All outputs 0.40 IIZ Input current for outputs in high D[15:0], HD[7:0] Bus holders enabled, DVDD = MAX, VI = VSS to DVDD –175 175 µA IIZ out uts in high impedance All other inputs DVDD = MAX, VO = VSS to DVDD –5 5 µA X2/CLKIN –40 40 TRST With internal pulldown –5 300 Input current HPIENA With internal pulldown (VI =VSS –5 300 II Input current TMS, TCK, TDI, HPI} With internal pullups, HPIENA = 0 (VI = VSS to DVDD) –300 5 µA All other input-only 5 5 All other in ut only pins –5 5 IDDC Supply current, core CPU CVDD = 1.8 V, fclock = 80 MHz,w TC = 25°C 35 mA I Supply current pins fclock = 80 MHz,w DVDD = 1.71 to 1.89 V 12 mA IDDP Supply current, pins fclock = 80 MHz,w TC = 25°C DVDD = 1.9 to 3.6 V 27 mA IDD Supply current, IDLE2 PLL × 1 mode, 80 MHz input 1.6 mA IDD Su ly current, standby IDLE3 Divide-by-two mode, CLKIN stopped 20 µA Ci Input capacitance 5 pF Co Output capacitance 5 pF † All values are typical unless otherwise specified. ‡ HPI input signals except for HPIENA. § Clock mode: PLL × 1 with external source Timing parameters provided in this document are measured using the following load circuit on all device output pins. |
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