TMS320UC5402 datasheet(40/63 Pages) TI

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TMS320UC5402

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS096A – APRIL 1999 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a

parallel I/O port write

(IOSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 15)

PARAMETER

MIN

MAX

UNIT

td(CLKL-A)

Delay time, CLKOUT low to address valid

td(CLKH-ISTRBL)

Delay time, CLKOUT high to IOSTRB low

–2

td(CLKH-D)IOW

Delay time, CLKOUT high to write data valid

H–5

H+14

td(CLKH-ISTRBH)

Delay time, CLKOUT high to IOSTRB high

–2

td(CLKL-RWL)

Delay time, CLKOUT low to R/W low

td(CLKL-RWH)

Delay time, CLKOUT low to R/W high

th(A)IOW

Hold time, address valid after CLKOUT low

th(D)IOW

Hold time, write data after IOSTRB high

H–3

H+9

tsu(D)IOSTRBH

Setup time, write data before IOSTRB high

H–9

H+1

tsu(A)IOSTRBL

Setup time, address valid before IOSTRB low

H–1

H+1

† Address and IS timings are included in timings referenced as address.

R/W

IOSTRB

D[15:0]

A[19:0]

CLKOUT

td(CLKH-ISTRBH)

th(A)IOW

th(D)IOW

td(CLKH-D)IOW

td(CLKH-ISTRBL)

td(CLKL-A)

td(CLKL-RWL)

td(CLKL-RWH)

tsu(A)IOSTRBL

tsu(D)IOSTRBH

NOTE A: A[19:16] are always driven low during I/O accesses.

Figure 15. Parallel I/O Port Write (IOSTRB = 0)

TMS320UC5402 Datasheet(PDF) 40 Page - Texas Instruments

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