Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

TMS320UC5402 Datasheet(PDF) 28 Page - Texas Instruments

Part # TMS320UC5402
Description  FIXED-POINT DIGITAL SIGNAL PROCESSOR
PDF  63 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320UC5402 Datasheet(HTML) 28 Page - Texas Instruments

Back Button TMS320UC5402 Datasheet HTML 24Page - Texas Instruments TMS320UC5402 Datasheet HTML 25Page - Texas Instruments TMS320UC5402 Datasheet HTML 26Page - Texas Instruments TMS320UC5402 Datasheet HTML 27Page - Texas Instruments TMS320UC5402 Datasheet HTML 28Page - Texas Instruments TMS320UC5402 Datasheet HTML 29Page - Texas Instruments TMS320UC5402 Datasheet HTML 30Page - Texas Instruments TMS320UC5402 Datasheet HTML 31Page - Texas Instruments TMS320UC5402 Datasheet HTML 32Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 28 / 63 page
background image
TMS320UC5402
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS096A – APRIL 1999 – REVISED DECEMBER 1999
28
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
interrupts (continued)
The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in Figure 7.
15–14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RES
DMAC5
DMAC4
BXINT1
or
DMAC3
BRINT1
or
DMAC2
HPINT
INT3
TINT1
or
DMAC1
DMAC0
BXINT0
BRINT0
TINT0
INT2
INT1
INT0
Figure 7. IFR and IMR Registers
Table 14. IFR and IMR Register Bit Fields
BIT
FUNCTION
NUMBER
NAME
FUNCTION
15–14
–
Reserved for future expansion
13
DMAC5
DMA channel 5 interrupt flag/mask bit
12
DMAC4
DMA channel 4 interrupt flag/mask bit
11
BXINT1/DMAC3
This bit can be configured as either the McBSP1 transmit interrupt flag/mask bit, or the DMA
channel 3 interrupt flag/mask bit. The selection is made in the DMPREC register.
10
BRINT1/DMAC2
This bit can be configured as either the McBSP1 receive interrupt flag/mask bit, or the DMA
channel 2 interrupt flag/mask bit. The selection is made in the DMPREC register.
9
HPINT
Host to ’54x interrupt flag/mask
8
INT3
External interrupt 3 flag/mask
7
TINT1/DMAC1
This bit can be configured as either the timer1 interrupt flag/mask bit, or the DMA channel 1
interrupt flag/mask bit. The selection is made in the DMPREC register.
6
DMAC0
DMA channel 0 interrupt flag/mask bit
5
BXINT0
McBSP0 transmit interrupt flag/mask bit
4
BRINT0
McBSP0 receive interrupt flag/mask bit
3
TINT0
Timer 0 interrupt flag/mask bit
2
INT2
External interrupt 2 flag/mask bit
1
INT1
External interrupt 1 flag/mask bit
0
INT0
External interrupt 0 flag/mask bit



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com