XIO2001 datasheet(60/131 Pages) TI

60 / 131 page

4.26 Capabilities Pointer Register

4.27 Interrupt Line Register

4.28 Interrupt Pin Register

XIO2001 PCI Express™ to PCI Bus Translation Bridge

SCPS212B – MAY 2009 – REVISED JULY 2009

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Table 4-16. I/O Limit Upper 16-Bit Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

I/O limit upper 16 bits. Defines the upper 16 bits of the top address of the I/O address range that

15:0

IOLIMIT

determines when to forward I/O transactions downstream. These bits correspond to address bits

[31:20] in the I/O address. The lower 20 bits are assumed to be FFFFFh.

This read-only register provides a pointer into the PCI configuration header where the PCI power

management block resides. Since the PCI power management registers begin at 40h, this register is

hardwired to 40h.

PCI register offset:

34h

Read-only

Default value:

40h

BIT NUMBER

RESET STATE

This read/write register is programmed by the system and indicates to the software which interrupt line the

bridge has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not

yet been assigned to the function. Since the bridge does not generate interrupts internally, this register is

a scratch pad register.

PCI register offset:

3Ch

Read/Write

Default value:

FFh

BIT NUMBER

RESET STATE

The interrupt pin register is read-only 00h indicating that the bridge does not generate internal interrupts.

While the bridge does not generate internal interrupts, it does forward interrupts from the secondary

interface to the primary interface.

PCI register offset:

3Dh

Read-only

Default value:

00h

BIT NUMBER

RESET STATE

Classic PCI Configuration Space

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