XIO2001 datasheet(22/131 Pages) TI

22 / 131 page

XIO2001 PCI Express™ to PCI Bus Translation Bridge

SCPS212B – MAY 2009 – REVISED JULY 2009

www.ti.com

Table 2-6. Combined Power Output Terminals

I/O

EXTERNAL

SIGNAL

ZGU BALL #

ZAJ BALL #

DESCRIPTION

TYPE

PARTS

VDD_15_COMB

L13

N13

Internally-combined 1.5-V main and VAUX power output for

external bypass capacitor filtering. Supplies all internal 1.5-V

Feed

Bypass

circuitry powered by VAUX.

through

capacitors

Caution: Do not use this terminal to supply external power

to other devices.

VDD_33_COMB

J13

K12

Internally-combined 3.3-V main and VAUX power output for

external bypass capacitor filtering. Supplies all internal 3.3-V

Feed

Bypass

circuitry powered by VAUX.

through

capacitors

Caution: Do not use this terminal to supply external power

to other devices.

VDD_33_COMBIO

K11

Internally-combined 3.3-V main and VAUX power output for

external bypass capacitor filtering. Supplies all internal 3.3-V

Feed

Bypass

input/output circuitry powered by VAUX.

through

capacitors

Caution: Do not use this terminal to supply external power

to other devices.

Table 2-7. PCI Express Terminals

ZGU

ZAJ

I/O

CELL

CLAMP

EXTERNAL

SIGNAL

DESCRIPTION

BALL #

TYPE

RAIL

PARTS

CLKREQ

D11

VDD_33_

Clock request. When asserted low, requests

CMOS

COMBIO

upstream device start clock in cases where

clock may be removed in L1.

–

Note: Since CLKREQ is an open-drain output

buffer,

system

side

pullup

resistor

required.

PERST

H11

VDD_33_

PCI Express reset input. The PERST signal

CMOS

COMBIO

identifies when the system power is stable and

–

generates an internal power on reset.

Note: The PERST input buffer has hysteresis.

REFCLK12

B13

A13

VDD_33

Reference clock select. This terminal selects

5_SEL

CMOS

the reference clock input.

Pullup or

0 = 100-MHz differential common reference

pulldown

clock used.

resistor

1 = 125-MHz single-ended, reference clock

used.

REFCLK+

C13

HS DIFF

VDD_33

Reference clock. REFCLK+ and REFCLK–

comprise the differential input pair for the

–

100-MHz system reference clock. For a

single-ended, 125-MHz system reference

clock, use the REFCLK+ input.

REFCLK–

C12

B13

HS DIFF

VDD_33

Reference clock. REFCLK+ and REFCLK–

Capacitor

comprise the differential input pair for the

for VSS for

100-MHz system reference clock. For a

single-

single-ended, 125-MHz system reference

ended node clock, attach a capacitor from REFCLK– to

VSS.

REF0_PCIE

K12

M13

I/O

BIAS

–

External reference resistor + and – terminals

REF1_PCIE

K13

L13

for setting TX driver current. An external

resistance of 14,532-

Ω is connected between

External

REF0_PCIE and REF1_PCIE terminals. To

resistor

eliminate the need for a custom resistor, two

series resistors are recommended: a 14.3-k

Ω,

1% resistor and a 232-

Ω, 1% resistor.

RXP

E13

HS DIFF

VSS

High-speed receive pair. RXP and RXN

RXN

E12

D13

–

comprise the differential receive pair for the

single PCI Express lane supported.

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