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XIO2001 Datasheet(PDF) 24 Page - Texas Instruments |
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XIO2001 Datasheet(HTML) 24 Page - Texas Instruments |
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24 / 131 page  XIO2001 PCI Express™ to PCI Bus Translation Bridge SCPS212B – MAY 2009 – REVISED JULY 2009 www.ti.com Table 2-8. PCI System Terminals (continued) ZGU ZAJ I/O CELL CLAMP EXTERNAL SIGNAL DESCRIPTION BALL # BALL # TYPE TYPE RAIL PARTS FRAME J02 J01 I/O PCI Bus PCIR Pullup PCI frame resistor per PCI spec GNT5 B10 B11 O PCI Bus PCIR PCI grant outputs. These signals are used for GNT4 A11 B10 arbitration when the PCI bus is the secondary GNT3 B09 B09 bus and an external arbiter is not used. GNT0 – GNT2 B08 B08 is used as the REQ for the bridge when an GNT1 C06 A06 external arbiter is used. GNT0 A05 A05 INTA M06 N06 I PCI Bus PCIR PCI interrupts A–D. These signals are interrupt Pullup INTB N06 L06 inputs to the bridge on the secondary PCI bus. resistor per INTC M07 M07 PCI spec INTD L07 N07 IRDY J01 H03 I/O PCI Bus PCIR Pullup PCI initiator ready resistor per PCI spec LOCK M08 N08 I/O PCI Bus PCIR This terminal functions as PCI LOCK when bit 12 (LOCK_EN) is set in the general control Pullup register (see Section 4.65). resistor per Note: In lock mode, an external pullup resistor PCI spec is required to prevent the LOCK signal from floating. M66EN L06 M06 I PCI Bus PCIR 66-MHz mode enable 0 = Secondary PCI bus and clock outputs Pullup operate at 33 MHz. If PCLK66_SEL is low then resistor per the frequency will be 25 MHz. PCI spec 1 = Secondary PCI bus and clock outputs operate at 66 MHz. If PCLK66_SEL is low then the frequency will be 50 MHz. PAR F01 G01 I/O PCI Bus PCIR – PCI bus parity PERR G02 G03 I/O PCI Bus PCIR Pullup PCI parity error resistor per PCI spec PME L12 M12 I LV VDD_33_ Pullup resistor per PCI spec PCI power CMOS COMBIO management event. This terminal may be used Pullup to detect PME events from a PCI device on the resistor per secondary bus. PCI spec Note: The PME input buffer has hysteresis. REQ5 A12 C09 I PCI Bus PCIR PCI request inputs. These signals are used for REQ4 C09 A09 If unused, a arbitration on the secondary PCI bus when an REQ3 C08 C08 weak pullup external arbiter is not used. REQ0 is used as REQ2 A08 C07 resistor per the GNT for the bridge when an external REQ1 A06 C06 PCI spec arbiter is used. REQ0 A04 A04 PRST N07 L07 O PCI Bus PCIR PCI reset. This terminal is an output to the – secondary PCI bus. SERR G03 G02 I/O PCI Bus PCIR Pullup PCI system error resistor per PCI spec STOP G01 H01 I/O PCI Bus PCIR Pullup PCI stop resistor per PCI spec TRDY H01 J02 I/O PCI Bus PCIR Pullup PCI target ready resistor per PCI spec Overview 24 Submit Documentation Feedback |
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