XIO2001 datasheet(32/131 Pages) TI

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3.3.2

Beacon

3.3.3

Wake

3.3.4

Initial Flow Control Credits

3.3.5

PCI Express Message Transactions

XIO2001 PCI Express™ to PCI Bus Translation Bridge

SCPS212B – MAY 2009 – REVISED JULY 2009

www.ti.com

The bridge supports the PCI Express in-band beacon feature. Beacon is driven on the upstream PCI

Express link by the bridge to request the reapplication of main power when in the L2 link state. To enable

the beacon feature, bit 10 (BEACON_ENABLE) in the general control register at offset D4h is asserted.

See Section 4.65, General Control Register, for details.

If the bridge is in the L2 link state and beacon is enabled, when a secondary PCI bus device asserts PME,

then the bridge outputs the beacon signal on the upstream PCI Express link. The beacon signal frequency

is approximately 500 kHz

± 50% with a differential peak-to-peak amplitude of 500 mV and no

de-emphasis. Once the beacon is activated, the bridge continues to send the beacon signal until main

power is restored as indicated by PERST going inactive. At this time, the beacon signal is deactivated.

The bridge supports the PCI Express sideband WAKE feature. WAKE is an active low signal driven by the

bridge to request the reapplication of main power when in the L2 link state. Since WAKE is an

open-collector output, a system-side pullup resistor is required to prevent the signal from floating.

When the bridge is in the L2 link state and PME is received from a device on the secondary PCI bus, the

WAKE signal is asserted low as a wakeup mechanism. Once WAKE is asserted, the bridge drives the

signal low until main power is restored as indicated by PERST going inactive. At this time, WAKE is

deasserted.

The bridge flow control credits are initialized using the rules defined in the PCI Express Base

Specification. Table 3-2 identifies the initial flow control credit advertisement for the bridge.

Table 3-2. Initial Flow Control Credit Advertisements

CREDIT TYPE

INITIAL ADVERTISEMENT

Posted request headers (PH)

Posted request data (PD)

128

Non-posted header (NPH)

Non-posted data (NPD)

Completion header (CPLH)

0 (infinite)

Completion data (CPLD)

0 (infinite)

PCI Express messages are both initiated and received by the bridge. Table 3-3 outlines message support

within the bridge.

Table 3-3. Messages Supported by the Bridge

MESSAGE

SUPPORTED

BRIDGE ACTION

Assert_INTx

Yes

Transmitted upstream

Deassert_INTx

Yes

Transmitted upstream

PM_Active_State_Nak

Yes

Received and processed

PM_PME

Yes

Transmitted upstream

PME_Turn_Off

Yes

Received and processed

PME_TO_Ack

Yes

Transmitted upstream

ERR_COR

Yes

Transmitted upstream

ERR_NONFATAL

Yes

Transmitted upstream

ERR_FATAL

Yes

Transmitted upstream

Set_Slot_Power_Limit

Yes

Received and processed

Feature/Protocol Descriptions

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