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MAX11040 Datasheet(PDF) 11 Page - Maxim Integrated Products |
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MAX11040 Datasheet(HTML) 11 Page - Maxim Integrated Products |
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11 / 31 page ![]() 24-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADC ______________________________________________________________________________________ 11 Digital Filter The MAX11040 contains an on-chip digital lowpass fil- ter that processes the data stream from each modulator and generates the high-resolution output data. The low- pass filter frequency response is determined by the programmable output data rate. At the nominal 16ksps output data rate, the -3dB bandwidth of the filter is 3.4kHz. The passband flatness is better than ±0.1dB from 0 to 1.74kHz. The notches are located at 5.75kHz and 7.195kHz. These frequencies scale linearly with the output data rate. See Figure 2 and Table 1 for the fre- quency response at different data rates. Since the transfer function of a digital filter is repeatable and predictable, it is possible to correct for frequency- dependent attenuation in downstream software. See the Compensating for the Rolloff of the Digital Filter in a Typical FFT Analysis section. The transfer function is defined by the following equation: where: Gain is the filter gain. fAIN is the analog input frequency. fSAMPLE is the programmed output data rate, nomi- nally 16kHz. fXINCLOCK is the clock frequency at XIN, nominally 24.576MHz. FIR_Gain (fAIN) is the normalized gain of the FIR fil- ter with the following filter coefficients, as a function of the analog input frequency fAIN. These coeffi- cients are applied at the output data rate: + 0.021484375 - 0.072265625 - 0.035156250 + 0.304687500 + 0.539062500 + 0.304687500 - 0.035156250 - 0.072265625 + 0.021484375 Latency The digital filter determines the latency of the MAX11040. Latency is defined as the time between the effective point in time that a sample is taken and when the resulting digital data is available for reading. The latency of the converter is specified by the follow- ing equation: Latency = (6 x tDOUT) + (PHI x 1.3µs) + 30µs where tDOUT is the data output period (inverse of the programmed sample rate), determined by fXINCLOCK and the selected output data rate, and PHI is the pro- grammed sampling instant delay for the channel in question (0 ≤ PHI ≤ 255). The latency is approximately 405µs at 16ksps. Gain f f f f f FIR Gain f AIN AIN SAMPLE AIN XINCLOCK AIN () sin sin _( ) = × ⎛ ⎝⎜ ⎞ ⎠⎟ × ⎛ ⎝⎜ ⎞ ⎠⎟ ⎛ ⎝ ⎜ ⎜ ⎜ ⎜⎜ ⎞ ⎠ ⎟ ⎟ ⎟ ⎟⎟ () π π 3 Table 1. Bandwidth vs. Output Data Rate OUTPUT DATA RATE (ksps) -3dB BANDWIDTH (kHz) -0.1dB BANDWIDTH (kHz) 0.5 0.11 0.05 1 0.21 0.11 2 0.42 0.22 4 0.85 0.43 8 1.69 0.87 10 2.11 1.09 12 2.54 1.31 16 3.38 1.74 32 6.78 3.48 64 13.5 6.96 fAIN/fSAMPLE 0.24 0.20 0.16 0.12 0.8 0.4 -5 -4 -3 -2 -1 0 1 -6 0 0.28 Figure 2. Digital Filter Response |
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