MAX11040 datasheet(14/31 Pages) MAXIM

14 / 31 page

24-Bit, 4-Channel, Simultaneous-Sampling,

Cascadable, Sigma-Delta ADC

______________________________________________________________________________________

|AIN+ - AIN-|

FULL SCALE

(|0.88VREF|)

FAULT DETECTION

THRESHOLD

(VPFT OR |VNFT|)

FAULT

OVRFLW

RECOVERY TIME

LATENCY

DIGITAL OUTPUT

DATA AT DOUT

LATENCY

Figure 5. Low-Frequency Analog Input Overvoltage Detection and Recovery

Reference

The MAX11040 operates with either a +2.5V internal

bandgap reference or an external reference source

between +2.3V and +2.7V applied at REFIO. Bypass

REFIO and each REF_ to AGND with a 1µF capacitor.

The reference voltage sets the positive and negative

full-scale voltage according to the following formula:

±FS = ±0.88 VREFIO

The reference voltage at REFIO (external or internal) is

individually buffered to generate the reference voltages

at REF0 to REF3 (see Figure 6.) These independent

buffers minimize the potential for crosstalk between

each of the internal ADCs.

Serial Interface

The MAX11040 interface is fully compatible with

SPI/DSP standard serial interfaces (compatible with SPI

modes CPOL = 0, CPHA = 0 and CPOL = 1, and CPHA

= 1). The serial interface provides access to four on-

chip registers: Sampling Instant Control register (32

bits), Data Rate Control register (16 bits), Configuration

interface commands begin with a command byte,

which addresses a specific register, followed by data

bytes with a data length that depends on the specific

ed (see Figures 7, 8, and the

Registers section).

The serial interface consists of eight signals: CS,

SCLK, DIN, DOUT, CASCIN, CASCOUT, DRDYIN,

and DRDYOUT. CASCIN, CASCOUT, DRDYIN, and

DRDYOUT are used for daisy chaining multiple devices

together. See the

Multiple Device Connection section

for details on how to connect CASCIN, CASCOUT,

+2.5V

REFERENCE

REFIO

REF3

REF2

REF1

REF0

Figure 6. REFIO Input

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