MAX11040 datasheet(15/31 Pages) MAXIM

15 / 31 page

24-Bit, 4-Channel, Simultaneous-Sampling,

Cascadable, Sigma-Delta ADC

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DRDYIN, and DRDYOUT. For single-device applications,

connect CASCIN and DRDYIN to DGND and drive CS

low to transfer data in and out of the MAX11040. With

DRDYIN low, a falling edge at the data ready signal out-

put (DRDYOUT) indicates that new conversion results

are available for reading in the 96-bit data register. A

falling edge on SCLK clocks in data at DIN. Data at

DOUT changes on the rising edge of SCLK and is valid

on the falling edge of SCLK. DIN and DOUT are trans-

ferred MSB first. Drive CS high to disable the interface

and place DOUT in a high-impedance state.

An interface operation with the MAX11040 takes effect

on the last rising edge of SCLK. If CS goes high before

the complete transfer, the write is ignored. Every data

transfer is initiated by the command byte. The com-

mand byte consists of an R/W bit and 7 address bits

(see Table 2.) Figures 7 and 8 show the timing for read

and write operations, respectively.

DIN

SCLK

DOUT

HIGH-Z

DATA LENGTH (NUMBER OF BYTES) DEPENDS

ON THE REGISTER BEING READ (SEE TABLE 2)

COMMAND ADDRESS

tSU

tPW

tSCP

tHD

tDOT

tDOE

tDOD

B7 B6 B5 B4 B3 B2 B1 B0

DRDYOUT

DRDYIN

tPW

tCSW

tSU

HIGH-Z

R/W

tDRDY

DATA READY

Figure 7. General Read-Operation Timing Diagram

DIN

SCLK

DOUT

HIGH-Z

DATA LENGTH (NUMBER OF BYTES) DEPENDS ON

THE REGISTER BEING WRITTEN (SEE TABLE 2)

A6 A5 A4 A3 A2 A1 A0

B5 B4 B3 B2 B1

COMMAND ADDRESS

tSU

tHD

tSCP

tPW

tCSW

tSU

R/W

Figure 8. General Write-Operation Timing Diagram

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