MAX11040 datasheet(25/31 Pages) MAXIM

25 / 31 page

24-Bit, 4-Channel, Simultaneous-Sampling,

Cascadable, Sigma-Delta ADC

______________________________________________________________________________________

C for Simultaneous

Sampling with Multiple Devices

The SYNC input permits multiple devices to sample

simultaneously. The mismatch between the power-up

reset of multiple devices causes the devices to begin

conversion at different times. After a falling edge on the

SYNC input, the device completes the current conver-

sion and then synchronizes subsequent conversions

(see Figure 15).

Upon a SYNC falling edge, the MAX11040 measures the

time between the SYNC falling edge to the preceding

DRDYOUT falling edge, waits until the next DRDYOUT

falling edge, then pauses the ADC for the measured

amount of time. Figure 15 shows an example where the

converter is regularly sampling the input and producing

a DRDYOUT with a period tS. The effect of a SYNC

falling edge as shown in Figure 15 is described in

sequence below:

1) A SYNC falling edge is issued two XIN clock cycles

after the DRDYOUT event 2.

2) The converter remembers the two XIN clock cycles,

and completes the current sample, issuing DRDYOUT

event 3 a period of tS after DRDYOUT event 2.

3) Then, the converter pauses for the remembered time

period, two XIN clock cycles for this example.

4) Correspondingly, DRDYOUT event 4 is issued two

XIN cycles later than it would have without the

SYNC falling edge.

5) The process continues as normal with DRDYOUT

event 5 appearing tS after DRDYOUT event 4.

XIN

NOTE: THE LATENCY IS NOT TO SCALE.

DRDYOUT

SYNC

AIN_

MEASURE

PAUSE

DELAY 2

CYCLES

Figure 15. Effect of a SYNC Falling Edge

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