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AD5293

Rev. 0 | Page 16 of 20

RDAC ARCHITECTURE

To achieve optimum cost performance, Analog Devices, Inc., has

patented the RDAC segmentation architecture for all the digital

potentiometers. In particular, the AD5293 employs a three-stage

segmentation approach, as shown in Figure 33. The AD5293 wiper

switch is designed with transmission gate CMOS topology and

with the gate voltage derived from VDD.

10-BIT

ADDRESS

DECODER

Figure 33. Simplified RDAC Circuit

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation—1% Resistor Tolerance

The AD5293 operates in rheostat mode when only two termi-

nals are used as a variable resistor. The unused terminal can be

left floating or can be tied to the W terminal as shown in Figure 34.

Figure 34. Rheostat Mode Configuration

The nominal resistance between Terminal A and Terminal B,

RAB, is available in 20 kΩ and has 1024 tap points that are

accessed by the wiper terminal. The 10-bit data in the RDAC

latch is decoded to select one of the 1024 possible wiper settings.

The AD5293 contains an internal ±1% resistor tolerance cali-

bration feature that can be enabled or disabled (enabled by

default) by programming Bit C2 of the control register (see

Table 9 and Table 10).

The digitally programmed output resistance between the W

terminal and the A terminal, RWA, and the W terminal and

B terminal, RWB, is calibrated to give a maximum of ±1%

absolute resistance error over both the full supply and

temperature ranges. As a result, the general equation for

determining the digitally programmed output resistance

between the W terminal and B terminal is

1024

)

(

(1)

where:

is the decimal equivalent of the binary code loaded in the

10-bit RDAC register.

RAB

is the end-to-end resistance.

Similar to the mechanical potentiometer, the resistance of the

RDAC between the W terminal and the A terminal also

produces a digitally controlled complementary resistance, RWA.

RWA is also calibrated to give a maximum of 1% absolute

resistance error. RWA starts at the maximum resistance value and

decreases as the data loaded into the latch increases. The

general equation for this operation is

−

1024

)

(

(2)

where:

is the decimal equivalent of the binary code loaded in the

10-bit RDAC register.

RAB

is the end-to-end resistance.

In the zero-scale condition, a finite total wiper resistance of 120 Ω

is present. Regardless of the setting in which the part is operating,

care should be taken to limit the current between the A terminal

and B terminal, the W terminal and A terminal, and the W termi-

nal and B terminal to the maximum continuous current of ±3 mA

or to the pulse current specified in Table 4. Otherwise, degradation,

or possible destruction of the internal switch contact, can occur.

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at the

wiper-to-B terminal and the wiper-to-A terminal that is pro-

portional to the input voltage at A to B, as shown in Figure 35.

Unlike the polarity of VDD to GND, which must be positive,

voltage across A to B, W to A, and W to B can be at either

polarity.

VIN

VOUT

Figure 35. Potentiometer Mode Configuration

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