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AD5293

Rev. 0 | Page 17 of 20

TERMINAL VOLTAGE OPERATING RANGE

If ignoring the effect of the wiper resistance for simplicity,

connecting the A terminal to 30 V and the B terminal to ground

produces an output voltage at the Wiper W to Terminal B that

ranges from 0 V to 30 V − 1 LSB. Each LSB of voltage is equal to

the voltage applied across the A terminal and B terminal, divided

by the 1024 positions of the potentiometer divider. The general

equation defining the output voltage at VW, with respect to

ground for any valid input voltage applied to Terminal A and

Terminal B, is

The positive VDD and negative VSS power supplies of the AD5293

define the boundary conditions for proper 3-terminal, digital

potentiometer operation. Supply signals present on the A, B,

and W terminals that exceed VDD or VSS are clamped by the

internal forward-biased diodes (see Figure 37).

−

1024

)

(

(3)

VSS

VDD

To optimize the wiper position update rate when in voltage

divider mode, it is recommended that the internal ±1% resistor

tolerance calibration feature be disabled by programming Bit C2

of the control register (see Table 9 and Table 10).

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike

when the part is in the rheostat mode, the output voltage is

dependent mainly on the ratio of the internal resistors, RWA and

RWB, not on the absolute values. Therefore, the temperature drift

reduces to 5 ppm/°C.

Figure 37. Maximum Terminal Voltages Set by VDD and VSS

The ground pin of the AD5293 is primarily used as a digital

ground reference. To minimize the digital ground bounce, the

AD5293 ground pin should be joined remotely to common

ground. The digital input control signals to the AD5293 must be

referenced to the device ground pin (GND) to satisfy the logic

level defined in the Specifications section.

EXT_CAP CAPACITOR

A 1 μF capacitor to GND must be connected to the EXT_CAP

pin (see Figure 36) on power-up and throughout the operation

of the AD5293. This capacitor must have a voltage rating of ≥7 V.

Power-Up Sequence

Because there are diodes to limit the voltage compliance at the

A, B, and W terminals (see Figure 37), it is important to power

VDD and VSS first, before applying any voltage to the A, B, and W

terminals. Otherwise, the diode is forward-biased such that VDD

and VSS are powered up unintentionally. The ideal power-up

sequence is GND, VSS, VLOGIC, VDD, the digital inputs, and then

VA, VB, and VW. The order of powering up VA, VB, VW, and the

digital inputs is not important, as long as they are powered after

VDD, VSS, and VLOGIC.

AD5293

GND

1µF

EXT_CAP

Figure 36. Hardware Setup for the EXT_CAP Pin

Regardless of the power-up sequence and the ramp rates of the

power supplies, the power-on preset activates after VLOGIC is

powered, restoring midscale to the RDAC register.

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