SN8P2613 datasheet(27/102 Pages) SONIX

27 / 102 page

SN8P2610 Series

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 27

Version 1.3

2.1.4.5

PROGRAM FLAG

The PFLAG register contains the arithmetic status of ALU operation, system reset status and LVD detecting status.

NT0, NPD bits indicate system reset status including power on reset, LVD reset, reset by external pin active and

watchdog reset. C, DC, Z bits indicate the result status of ALU operation. LVD24, LVD36 bits indicate LVD detecting

power voltage status.

086H

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PFLAG

NT0

NPD

LVD36

LVD24

Read/Write

R/W

After reset

Bit [7:6]

NT0, NPD:

Reset status flag.

NT0

NPD

Reset Status

Watch-dog time out

Reserved

Reset by LVD

Reset by external Reset Pin

Bit 5

LVD36:

LVD 3.6V operating flag and only support LVD code option is LVD_H.

0 = Inactive (VDD > 3.6V).

1 = Active (VDD <= 3.6V).

Bit 4

LVD24:

LVD 2.4V operating flag and only support LVD code option is LVD_M.

0 = Inactive (VDD > 2.4V).

1 = Active (VDD <= 2.4V).

Bit 2

Carry flag

1 = Addition with carry, subtraction without borrowing, rotation with shifting out logic “1”, comparison result

≥ 0.

0 = Addition without carry, subtraction with borrowing signal, rotation with shifting out logic “0”, comparison

result < 0.

Bit 1

DC:

Decimal carry flag

1 = Addition with carry from low nibble, subtraction without borrow from high nibble.

0 = Addition without carry from low nibble, subtraction with borrow from high nibble.

Bit 0

Zero flag

1 = The result of an arithmetic/logic/branch operation is zero.

0 = The result of an arithmetic/logic/branch operation is not zero.

Note: Refer to instruction set table for detailed information of C, DC and Z flags.

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