點晶科技股份有限公司

SILICON TOUCH TECHNOLOGY INC.

DM164

8x3-CHANNEL CONSTANT CURRENT LED DRIVERS

Version:A.002

Page 10

Serial Data Interface

The DM164 includes a flexible data transfer interface. The data can be transferred from

DIN pin to the shift registers at either the rising edge of DCK or the falling edge of DCK

depending on the signal DCKPH. After all data are clocked in, a high level LTH signal can

transfer the serial data to the data latches (Level Sensitive). The serial data format can be

192-bit or 384-bit wide, depending on the operating mode of the device.

Operating Modes

The DM164 has two operating modes depending on the signal MSEL. Table 1 shows the

available operating modes. When MSEL = H, the device operates at the D&G mode. D&G

mode is used to set dot correction data and global brightness control data after IC power

up or any time. When MSEL = L, the device becomes GD mode. GD mode is used to set

grayscale PWM data after D&G mode.

Table 1. Two Operating Modes

MSEL

MODE

SHIFT REGISTER

H

Dot Correction Data & Global Brightness Control

Data Input Mode (D&G mode)

192-bit

L

Grayscale PWM Data Input Mode (GD mode)

384-bit

D&G Mode Data Format

At D&G mode, dot correction data of all channels and global brightness control data of

different colors are transferred into the chip at the same time. The complete dot correction

data format consists of 24 x 7-bit and the global brightness control data of three different

colors consists of 3 x 8-bit. The total shift registers width at D&G mode is 192-bit. All data

is clocked in with MSB first. Figure 1 shows the D&G mode data format.

IOUT00

DC0

IOUT00

DC6

‧‧‧

IOUT01

DC0

IOUT22

DC6

IOUT23

DC0

IOUT23

DC6

‧‧‧

MSB

191

24

185

184

30

31

GB_R7

GB_R0

23

LSB

0

16

‧‧‧

‧‧‧

‧‧‧

IOUT23

IOUT22~IOUT01

IOUT00

GLOBAL_R

GB_G7

GB_G0

GB_B7

‧‧‧

GB_B0

GLOBAL_G

GLOBAL_B

7

8

15

Figure 1. D&G Mode Data Format (D&G[191:0])

To operate the DM164 in D&G mode, MSEL must be set to high. The shift register width is

then set to 192-bit wide. The input data can be transferred at either the rising edge of DCK