點晶科技股份有限公司

SILICON TOUCH TECHNOLOGY INC.

DM164

8x3-CHANNEL CONSTANT CURRENT LED DRIVERS

Version:A.002

Page 11

or the falling edge of DCK by setting DCKPH to L or H. After all data are transferred into

the D&G mode shift registers, the D&G mode data can be latched from shift registers to

the data latches by a LTH signal at either D&G mode or GD mode. Figure 2 shows the

D&G mode data input timing chart.

DCKPH

MSEL

DIN

D&G[191]

DCK

DOUT

(DOUTPH=L)

DOUT

(DOUTPH=H)

LTH

123

192

GND

D&G mode

GD mode

D&G[190]

D&G[189]

D&G[0]

D&G[191]

D&G[191]

GD[383]

GD[382]

Figure 2. D&G Mode Data Input Timing Chart

GD Mode Data Format

At GD mode, the grayscale PWM data will be transferred to the shift registers. The

complete grayscale PWM data format consists of 24 x 16-bit. The total shift registers width

at GD mode is 384-bit. All grayscale PWM data is clocked in with MSB first. Figure 3

shows the GD mode data format.

IOUT

23-15

MSB

383

IOUT

23-0

‧‧‧

IOUT

00-15

IOUT

00-0

‧‧‧

IOUT

22-15

IOUT

01-0

‧‧‧

LSB

0

368

367

15

16

IOUT23

IOUT00

IOUT22 ~ IOUT01

IOUT

01-1

IOUT

22-14

366

17

Figure 3. GD Mode Data Format (GD[383:0])

When MSEL is set to low, the DM164 enters GD mode. The internal shift registers

changes to 384-bit wide. The input data can be transferred at either the rising edge of DCK

or the falling edge of DCK by setting DCKPH to L or H. After all data are transferred into

the GD mode shift registers, the GD mode data can be latched from shift registers to the

data latches by a LTH signal at GD mode only. Figure 4 shows the GD mode data input

timing chart.