MAX17021 datasheet(38/48 Pages) MAXIM

38 / 48 page

Power-Up Sequence (POR, UVLO)

The MAX17021/MAX17082/MAX17482 are enabled

when

SHDN is driven high (Figure 10). The internal ref-

erence powers up first. Once the reference exceeds its

UVLO threshold, the internal analog blocks are turned

on and masked by a 50μs one-shot delay. The PWM

controller is then enabled.

Power-on reset (POR) occurs when VCC rises above

approximately 2V, resetting the fault latch and prepar-

ing the controller for operation. The VCC UVLO circuitry

inhibits switching until VCC rises above 4.25V. The con-

troller powers up the reference once the system

enables the controller, VCC is above 4.25V, and SHDN

is driven high. With the reference in regulation, the con-

troller ramps the output voltage to the boot voltage

(1.2V for MAX17021 IMVP-6+ and 1.1V for MAX17082/

MAX17482 IMVP-6.5) at 1/8 the slew rate set by RTIME:

where dVTARGET/dt = 12.5mV/μs x 71.5kΩ/RTIME is the

slew rate. The soft-start circuitry does not use a variable

current limit, so full output current is available immediate-

ly.

CLKEN is pulled low approximately 60μs after the

MAX17021/MAX17082/MAX17482 reach the boot voltage

if PGDIN is high. At the same time, the MAX17021/

MAX17082/MAX17482 slew the output to the voltage set

at the VID inputs at the programmed slew rate. PWRGD

and PHASEGD become high impedance approximately

5ms after

CLKEN is pulled low. The MAX17021/

MAX17082/MAX17482 automatically use forced-PWM

operation during soft-start and soft-shutdown, regardless

of the DPRSLPVR and

PSI configuration.

For automatic startup, the battery voltage should be

present before VCC. If the controller attempts to bring

the output into regulation without the battery voltage

present, the fault latch trips. The controller remains shut

down until the fault latch is cleared by toggling

SHDN

or cycling the VCC power supply below 0.5V.

If the VCC voltage drops below 4.25V, the controller

assumes that there is not enough supply voltage to

make valid decisions. To protect the output from over-

voltage faults, the controller shuts down immediately

and forces a high-impedance output.

TRAN START

BOOT

TARGET

() =

()

Dual-Phase, Quick-PWM Controllers for

IMVP-6+/IMVP-6.5 CPU Core Power Supplies

______________________________________________________________________________________

FORCED PWM

tBLANK

μs TYP

tBLANK

μs TYP

tBLANK

5ms TYP

tBLANK

μs TYP

VID (D0–D6)

VCORE

VBOOT

PWRGD

INTERNAL

PWM CONTROL

PHASEGD

VCC

SOFT-START =

1/8 SLEW RATE SET

BY RTIME

SHDN

INVALID

CODE

INVALID

CODE

SKIP

FORCEDPWM

CLKEN

SOFT-SHUTDOWN =

1/8 SLEW RATE SET

BY RTIME

Figure 10. Power-Up and Shutdown Sequence Timing Diagram

MAX17021 Datasheet(PDF) 38 Page - Maxim Integrated Products

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