AS3525 datasheet(82/194 Pages) AMSCO

82 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

- 194

Table 65 NAF interrupt clear register

Name

Base

Default

NAFClear

AS3525_NAND_FLASH_BASE

0x0018

Clear Register

Offset 0x0024

The NAFClear register clears interrupt status information and re-enables interrupt

detection.

Bit

Bit Name

Default

Access

Bit Description

clear6

Reset of ‘FIFO error indication’ status bit

0: no action

1: bit 6 of NAFStatus is reset and interrupt 6 detection is

enabled

clear5

Reset of ‘FIFO full indication’ status bit

0: no action

1: bit 5 of NAFStatus is reset and interrupt 5 detection is

enabled

clear4

Reset of ‘FIFO high indication’ status bit

0: no action

1: bit 4 of NAFStatus is reset and interrupt 4 detection is

enabled

clear3

Reset of ‘FIFO low indication’ status bit

0:no action

1:bit 3 of NAFStatus is reset and interrupt 3 detection is

enabled

clear2

Reset of ‘NAFWords empty and Controller ready indication’

status bit

0:no action

1:bit 2 of NAFStatus is reset and interrupt 2 detection is

enabled

clear1

Reset of ‘Read/write strobe ready indication’ status bit

0: no action

1: bit 1 of NAFStatus is reset and interrupt 1 detection is

enabled

clear0

Reset of ‘Read/write strobe ready indication’ status bit

0:no action

1: bit 0 of NAFStatus is reset and interrupt 0 detection is

enabled

Table 66 NAF test register

Name

Base

Default

NAFTest

AS3525_NAND_FLASH_BASE

0x0000

Test Register

Offset 0x0028

The NAFTest register is used for functional tests of the FIFO.

Bit

Bit Name

Default

Access

Bit Description

datainvert

0: default mode

1: disables FIFO access by the internal controller => FIFO is

accessed by APB interface only

fifotest

0: default mode

1: data word both on FIFO input and output is inverted

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