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AS3525 Datasheet(PDF) 55 Page - ams AG |
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AS3525 Datasheet(HTML) 55 Page - ams AG |
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55 / 194 page  AS3525-A/-B C22O22 Data Sheet, Confidential © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 55 - 194 GPIO interrupt clear register Table 37 GPIO interrupt clear register Name Base Default GPIO1_IC GPIO2_IC GPIO3_IC GPIO4_IC AS3525_GPIO1_BASE AS3525_GPIO2_BASE AS3525_GPIO3_BASE AS3525_GPIO4_BASE 0xC80B0000 0xC80C0000 0xC80D0000 0xC80E0000 GPIO interrupt clear register Offset: 0x41C Setting a bit to HIGH in this register clears the corresponding interrupt edge detection logic register. Setting a bit to LOW in this register has no effect. This register is write- only. All bits are cleared by a reset. Bit Bit Name Default Access Bit Description 7:0 GPIO interrupt clear register 00000000 W 0: has no effect. 1: clears edge detection logic. GPIO mode control select register Table 38 GPIO2, GPIO3 mode control select register Name Base Default GPIO2_AFSEL GPIO3_AFSEL AS3525_GPIO2_BASE AS3525_GPIO3_BASE 0xC80C0000 0xC80D0000 GPIO mode control select register Offset: 0x420 Setting a bit to HIGH in this register selects DBOP control for the corresponding PrimeCell GPIO line. All bits are cleared by a reset. Bit Bit Name Default Access Bit Description 7:0 GPIO mode control select register 00000000 RW 0: enables software control mode on corresponding pin. Bits 1: enables DBOP control mode on corresponding pin. Table 39 GPIO1, GPIO4 mode control select register Name Base Default GPIO1_AFSEL GPIO4_AFSEL AS3525_GPIO1_BASE AS3525_GPIO4_BASE 0xC80B0000 0xC80E0000 GPIO mode control select register Offset: 0x420 Not used. If bit set to HIGH, the corresponding pin will be set to 1. Bit Bit Name Default Access Bit Description 7:0 GPIO mode control select register 00000000 RW Bits 0: enables software control mode on corresponding pin. Bits 1: corresponding pins set to 1. |
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