AS3525 datasheet(96/194 Pages) AMSCO

96 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

- 194

Table 79 UART Clock divider higher byte register

Name

Base

Default

UART_DHI_REG

AS3525_UART_BASE

0xC8110000

Clock divider higher byte register

Offset: 0x04

DLS set to 1

This register holds the higher byte of the decimal divisor value to calculate baud clock.

Bit

Bit Name

Default

Access

Bit Description

7:0

UART_DHI_REG

00000000

This register holds the higher byte of the decimal divisor value

to calculate baud clock.

Table 80 UART Interrupt enable register

Name

Base

Default

UART_INTEN_REG

AS3525_UART_BASE

0xC8110000

Interrupt enable register

Offset: 0x04

DLS set to 0

This register will enable the three types of interrupts. Setting the bits of this register to

logic 1 enables the selected interrupt.

Bit

Bit Name

Default

Access

Bit Description

7:3

Reserved

00000

These bits are reserved for future use.

lnStatusEn

This bit enables the “rxLineStatus” interrupt.

txDataEmptyEn

This bit enables the “txDataEmpty” interrupt.

rxDataRdyEn

This bit enables the “rxDataRdy” interrupt.

Table 81 UART Interrupt status register

Name

Base

Default

UART_INTSTATUS_REG

AS3525_UART_BASE

0xC8110000

Interrupt status register

Offset: 0x08

This register will give the status of the interrupt. Depending on the enabled interrupt

bits in the interrupt enable register (UART_INTEN_REG) different interrupts will be

generated and the status will be updated in this register. On sensing an interrupt the

software should read this register to get the status of the interrupt.

Bit

Bit Name

Default

Access

Bit Description

7:3

Reserved

00000

These bits are reserved for future use.

rxLineStatus

This interrupt is set on any error condition on the receive line.

There are four types of error possibilities. These error

conditions are set in bits 4:1 of the line status register

(UART_LNSTATUS_REG).

This bit is reset on a read of the line status register

(UART_LNSTATUS_REG).

txDataEmpty

In FIFO mode this bit is set when txFIFO is empty.

If FIFO mode is disabled this interrupt is set if the data register

(UART_DATA_REG (Tx)) is empty.

This bit will be reset on write to the data register

(UART_DATA_REG (Tx)).

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