 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AS3525 Datasheet(PDF) 83 Page - ams AG |
|
|
|||||||||||||||||||||||||||||
AS3525 Datasheet(HTML) 83 Page - ams AG |
|
|
83 / 194 page  AS3525-A/-B C22O22 Data Sheet, Confidential © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 83 - 194 7.3.12 DBOP - Data Block Output Port Purpose of this ARM APB peripheral module is a high-speed data output port that can support data transfer to various display controllers based on synchronous control interfaces. Programmability of polarity and timing of the generated control signals makes it possible to support various kinds of displays. Example of a supported display controller is the Hitachi HD77766R LCDE controller. From the programmers point of view the DBOP module can be serviced by DMA accesses. With the large size of the data FIFO and the programmable interrupt request conditions the overhead for SW is minimised. Simple read instructions to read for example a status register of the LCD controller are also supported. The usage of this cell results in a great performance boost compared to the standard ARM GPIO PrimeCell™ architecture. Features • APB bus interface • support for direct memory access (DMA) • data output FIFO with 128 words (32 bit wide) • 8 or 16 bit parallel data output (configurable) • 4 control outputs - flexible programming of the signal waveforms with respect to polarity and timing • programmable even/odd control output generation • 8 or 16 bit parallel data input register with programmable read strobe • programmable conditions for interrupt generation based on FIFO flags • usage of FIFO for simple division of APB clock domain and output clock domain • programmable data output rate in range of 0.05 to 4 MHz • APB Clock & DBOP Clocks are synchronous. Figure 33 DBOP Block Diagram Amba APB Interface PRESETn PSEL PENABLE PWRITE PADDR[11:2] PWDATA[31:0] PRDATA[7:0] PCLK Register Block DMA Interface DBOPDMASREQ DBOPDMABREQ DBOPDMACLR symetric FiFo Controller 32 32 Control Signal Generator dbop_clk c0 / xpb[0] c1 / xpb[1] c2 / xpb[2] c3 / xpb[3] dbop_d[7:0] / xpc[7:0] Din register FiFo push status FiFo pop status dinStrobe din[7:0] Interrupt Generator 8 dataValid Dout register lb_select, hb_select pop push Dual ported RAM 128x32 FiFo 128x32 DBOPIRQ DBOP dbop_d[11:8] / xpb[7:4] dbop_d[15:12] |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
