AS3525 datasheet(17/194 Pages) AMSCO

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AS3525-A/-B C22O22

Data Sheet, Confidential

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Revision 1.13

- 194

Detailed Functional Descriptions

This chapter contains detailed functional descriptions of all modules of the chip. Central microcontroller is an ARM-9, all

peripherals are connected to the AMBA bus which is divided into a AHB (advanced high speed bus) and APB (advanced

peripheral bus) part. All audio, power management and system monitoring functions are controlled via an I2C interface

(I2C audio master). This chapter includes also all detailed desciptions and performance values for these parts.

7.1

ARM922-T Processor Core

7.1.1 General

The ARM922T macrocell is a high-performance 32-bit RISC integer processor combining an ARM9TDMI™ processor core with:

•

8KB instruction cache and 8 KB data cache

•

Instruction and data Memory Management Unit (MMU)

•

Write buffer with 16 data words and 4 addresses

•

Advanced Microprocessor Bus Architecture (AMBA™) AHB interface

The ARM922T provides a high-performance processor solution for open systems requiring full virtual memory management and sophisticated

memory protection. The ARM922T processor core is capable of running at 250 MHz. The ARM922T hard macrocell has a very low power

consumption. The integrated cache helps to significantly reduce memory bandwith demands, improving performance and minimizing power

consumption.

At 250 MHz the ARM922T comsumes as little as 65 mW, making it ideal for high-performance battery operated audio or video applications.

The ARM core and associated bus structures are configured for little endian byte order (compatible with Windows CE™ and Symbian™ OS).

Table 10 ARM 922T characteristics

Cache (I/D)

MMU

AHB

Thumb

mW/MHz

MHz

8KB / 8KB

yes

0.25 @ 1.2 V

250

Features

•

32-bit RISC architecture (ARMv4T)

•

Harvard architecture with separated instruction (I) and data (D) caches with 8 KB each and 8-word line length

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Five stage pipeline (fetch, decode, execute, memory, write back) enabling high master clock speeds

•

32-bit ARM instruction set for maximum performance and flexibility

•

16-bit Thumb instruction set for increased code density

•

Enhanced ARM architecture V4 MMU to provide translation and access permission checks for instruction and data

addresses. With this MMU different operating systems (Windows CE, Symbian …) can be implemented.

•

Industry standard AMBA bus interface (AHB and APB)

•

Hard-macro implementation

•

The processor core clock frequency (FCLK) is programmable up to 250MHz and the ARM922 power consumption is directly

proportional to this clock frequency FCLK

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