AS3525 datasheet(98/194 Pages) AMSCO

98 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

- 194

Name

Base

Default

UART_LNCTL_REG

AS3525_UART_BASE

0xC8110000

Line control register

Offset: 0x10

This register controls the asynchronous data. Parameters in this register set the

transmit and receive character format, the data length, parity bit, stop bit length, etc.

Bit

Bit Name

Default

Access

Bit Description

DLS

Divisor Latch Select Bit. This bit is used to select Divisor Latch

registers.

1: Divisor Latch registers can be accessed. To access other

registers this bit should be zero.

breakCntl

1: Will cause a break condition to be transmitted, i.e. TX line is

pulled low. Normal transmission can be recovered once this bit

is cleared. Transmitter logic can be used as break timer.

stickParity

1: If this bit is set, along with parityEn a fixed parity bit will be

transmitted and expected. This fixed parity bit will be the

complement of the bit 4.

evenParity

0: Data byte along with parity bit will be sent and expected to

be odd parity.

1: Data byte along with the parity bit will be even parity.

parityEn

Enable parity bit.

0: Data byte will be transmitted and received without parity bit.

1: Will enable the parity bit at the end of the data byte.

stopBits

This bit decides how many stop bits should be sent along with

a data byte.

0: 1 stop bit transmitted

1: 2 stop bits transmitted if 6, 7 or 8 bit wordLenSel

1: 1.5 stop bits transmitted if 5 bit wordLenSel

Receiver will always check for one stop bit.

1:0

wordLenSel

These bits will select the number of data bits to be transmitted

and received.

00: 5 bits

01: 6 bits

10: 7 bits

11: 8 bits

Table 84 UART Line status register

Name

Base

Default

UART_LNSTATUS_REG

AS3525_UART_BASE

0xC8110000

Line status register

Offset: 0x14

This register holds the status information of the data transfer. It gives information about

the received data.

Bit

Bit Name

Default

Access

Bit Description

FIFODataError

1: This bit is set when any data character in the FIFO has

parity or framing error or break condition.

0: This bit is reset once the line status register

(LINE_STATUS_REG) is read.

Reserved

This bit is reserved for future use.

txHoldRegEmpty

This bit is associated with the txDataEmpty interrupt.

1: Indicates that there is no data in txFIFO or the data register

(UART_DATA_REG (Tx)). This bit is set once the data is

shifted out.

0: This bit is reset once data is written into the data register

(UART_DATA_REG (Tx)).

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