AS3525 datasheet(60/194 Pages) AMSCO

60 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

- 194

7.3.8.1

I2S Input Register Mapping

I2S Input Interface Registers

Table 42 I2S Input Interface Registers

Base Address

Offset

Note

I2SIN_CONTROL

AS3525_I2SIN_BASE

0x0000

Control register

I2SIN_MASK

AS3525_I2SIN_BASE

0x0004

Interrupt mask register

I2SIN_RAW_STATUS

AS3525_I2SIN_BASE

0x0008

Raw status register

I2SIN_STATUS

AS3525_I2SIN_BASE

0x000C

Status register

I2SIN_CLEAR

AS3525_I2SIN_BASE

0x0010

Interrupt clear register

I2SIN_DATA

AS3525_I2SIN_BASE

0x0014

Audio data register

I2SIN_SPDIF_STATUS

AS3525_I2SIN_BASE

0x0018

SPDIF status signals register

Table 43 I2S Input Control Register

Name

Base

Default

I2SIN_CONTROL

AS3525_I2SIN_BASE

0x04

Control register

Offset: 0x0000

12 bit wide read/write register containing the control bits of the I2SINIF.

Bit

Bit Name

Default

Access

Bit Description

DMA_req_en

R/W

DMA request enable

0: disable

1: enable

mclk_invert

R/W

Invert MCLK

0: disable (SCLK changes at MCLK’s falling edge)

1: enable (SCLK changes at MCLK’s rising edge)

9,8

i2s_clk_source

R/W

Define the source of SCLK and LRCK for I2SINIF

00: SCLK and LRCK from I2SOUTIF (used if AFE sends data)

01: SCLK and LRCK from external ADC device (outside AS3525)

10: SCLK and LRCK from SPDIF converter

11: SCLK and LRCK from I2SINIF’s clock controller

7,6

sdata_source

R/W

Define the source of SDATA for I2SINIF

00: SDATA from AFE

01: SDATA from external ADC device (outside AS3525)

10: SDATA from SPDIF converter

11: loopback SDATA from I2SOUTIF (test purpose)

14bit_mode

R/W

0: ADC data from FIFO transferred in two 32-bit words to

I2SIN_DATA (first left and then right data as indicated by the

stereo24_status bit)

1: ADC data from FIFO transferred in one 32-bit word to

I2SIN_DATA

sclk_idle

R/W

Enable/disable SCLK for I2SINIF

0: SCLK enabled

1: SCLK disabled

SDATA_valid

R/W

0: SDATA ignored at first SCLK edge (I2S standard)

1: valid SDATA at first SCLK edge

sclk_edge

R/W

0: data valid at negative edge of SCLK

1: data valid at positive edge of SCLK

1,0

osr

R/W

Oversampling rate (needed for generating sclk and lrck)

00: 128x

01: 256x

10: 512x

11: 128x

AS3525 Datasheet(PDF) 60 Page - ams AG

AS3525 Datasheet(HTML) 60 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL