AS3525 datasheet(109/194 Pages) AMSCO

109 / 194 page

AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

109

- 194

Table 27 Audio Clock Controller Register

Name

Base

Default

CGU_AUDIO

AS3525_CGU_BASE

0x00

Audio Clock Controller Register

Offset0x18

This register allows setting the audio clock to I2S input and output interface.

Bit

Bit Name

Default

Access

Bit Description

I2SI_MCLK2PAD_EN

R/W

I2S audio input clock (I2SI_MCLK) to PAD connection

enable

I2SI_MCLK_EN

R/W

I2S audio input clock (I2SI_MCLK) enable

22:14

I2SI_MCLK_DIV_SEL

[8:0]

0x0

R/W

I2Sin

audio

clock

division

ratio

div_i

1/(i2si_mclk_div_sel + 1)

13:12

ISI_MCLK_SEL[1:0]

0x0

R/W

I2SI_MCLK clkin select

00: clk_main

01: plla_fout

10: pllb_fout

11: reserved (clk_main)

I2SO_MCLK_EN

R/W

I2S audio output clock (I2SO_MCLK) enable

10:2

I2SO_MCLK_DIV_SEL

[8:0]

0x0

R/W

I2Sout

audio

clock

division

ratio

div_o

1/(i2so_mclk_div_sel + 1)

1:0

ISO_MCLK_SEL[1:0]

0x0

R/W

I2SO_MCLK clkin select

00: clk_main

01: plla_fout

10: pllb_fout

11: reserved (clk_main)

Note:

The clock gating bits in this register apply only to the audio clocks. To enable/disable the APB parts of the corresponding I2S IF

CGU_PERI has to be configured.

f(i2si_mclk) := f(I2SI_mclk clkin) * div_i;

f(i2so_mclk) := f(I2SO_mclk clkin) * div_o;

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