ADF4158

Rev. 0 | Page 13 of 36

DB31

CONTROL

BITS

20-BIT STEP WORD

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

000000

0

SSE1 S20

S19

S18

S17

S16

S15

S14

S13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

S1

C3(1) C2(1) C1(0)

STEP REGISTER (R6)

DB31

CONTROL

BITS

12-BIT DELAY START DIVIDER

RESERVED

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

00

000000

00000

RDF1 RD1

DC1 DSE1 DS12 DS11 DS10 DS9

DS8

DS7

DS6

DS5

DS4

DS3

DS2

DS1 C3(1) C2(1) C1(1)

DELAY REGISTER (R7)

NOTES

1. DBB = DOUBLE-BUFFERED BIT(S).

RESERVED

RESERVED

RESERVED

DB31

12-BIT CLOCK DIVIDER VALUE

CONTROL

BITS

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

LS1

0000

000

0

R2

R1

CK2

CK1

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

C3(1) C2(0) C1(0)

TEST REGISTER (R4)

CLK

DIV

MODE

READ-

BACK

TO

MUXOUT

0

0

00

DB31

16-BIT DEVIATION WORD

CONTROL

BITS

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

TR1

PR1

I2

I1

FRE1 R2E1 DS1

DO4 DO3

DO2 DO1

D16

D15

D14 D13

D12

D11

D10

D9

D8

D7

D6

D5

C3(1) C2(0) C1(1)

DEVIATION REGISTER (R5)

D4

D3

D2

D1

4-BIT DEV OFFSET

WORD

Figure 21. Register Summary 2