ADF4158

Rev. 0 | Page 17 of 36

DB31

12-BIT MOD DIVIDER

5-BIT R COUNTER

CP

CURRENT

SETTING

CONTROL

BITS

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

CR1 CPI4 CPI3 CPI2 CPI1

0

P1

U2

U1

R5

R4

R3

R2

R1

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

C3(0) C2(1) C1(0)

CR1

CYCLE SLIP

REDUCTION

0DISABLED

1ENABLED

U1

REFERENCE

DOUBLER

0DISABLED

1ENABLED

R5

R4

R3

R2

R1

R-COUNTER DIVIDE RATIO

00001

1

00010

2

00011

3

00100

4

....

.

....

.

....

.

11101

29

1111

.

30

11111

31

00000

32

U2

R DIVIDER

0

DISABLED

1ENABLED

P1

PRESCALER

04/5

18/9

ICP (mA)

CPI4

CPI3

CPI2

CPI1

5.1k

Ω

0

0

0

0

0.31

0

0

0

1

0.63

0

0

1

0

0.94

0

0

1

1

1.25

0

1

0

0

1.57

0

1

0

1

1.88

0

1

1

0

2.19

0

111

2.5

1

0

0

0

2.81

1

0

0

1

3.13

1

0

1

0

3.44

1

0

1

1

3.75

1

1

0

0

4.06

1

1

0

1

4.38

1

1

1

0

4.69

1

111

5

DBB

DBB

D12

D11

.......... D2

D1

12-BIT MOD DIVIDER VALUE

0

0

.......... 0

0

0

0

0

.......... 0

1

1

0

0

.......... 1

0

2

0

0

.......... 1

1

3

.

.

..........

.

.

.

.

.

..........

.

.

.

.

.

..........

.

.

.

1

1

.......... 0

0

4092

1

1

.......... 0

1

4093

1

1

.......... 1

0

4094

1

1

.......... 1

1

4095

NOTES

1. DBB = DOUBLE-BUFFERED BITS.

Figure 24. R-Divider Register (R2) Map