ADF4158

Rev. 0 | Page 14 of 36

FRAC/INT REGISTER (R0) MAP

With Register R0 DB[2:0] set to [0, 0, 0], the on-chip

FRAC/INT register is programmed as shown in Figure 22.

Ramp On

Setting DB31 to 1 enables the ramp, setting DB31 to 0 disables

the ramp.

MUXOUT Control

The on-chip multiplexer is controlled by DB[30:27] on the

ADF4158. See Figure 22 for the truth table.

12-Bit Integer Value (INT)

These 12 bits control what is loaded as the INT value. This is

used to determine the overall feedback division factor. It is used

in Equation 2. See the INT, FRAC, and R Relationship section

for more information.

12-Bit MSB Fractional Value (FRAC)

These 12 bits, along with Bits DB[27:15] in the LSB FRAC

register (Register R1), control what is loaded as the FRAC value

into the fractional interpolator. This is part of what determines

the overall feedback division factor. It is also used in Equation 2.

These 12 bits are the most significant bits (MSB) of the 25-bit

FRAC value, and Bits DB[27:15] in the LSB FRAC register

(Register R1) are the least significant bits (LSB). See the RF

Synthesizer: A Worked Example section for more information.

DB31

CONTROL

BITS

12-BIT MSB FRACTIONAL VALUE

(FRAC)

12-BIT INTEGER VALUE (INT)

MUXOUT

CONTROL

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R1

M4

M3

M2

M1

N12

N11

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

F25

F24

F23

F22

F21

F20

F19

F18

F17

F16

F15

F14 C3(0) C2(0) C1(0)

M4 M3 M2

M1

OUTPUT

0

0

0

0

THREE-STATE OUTPUT

000

1

001

0

DGND

001

1

R-DIVIDER OUTPUT

010

0

N-DIVIDER OUTPUT

0

1

0

1

RESERVED

0

1

1

0

DIGITAL LOCK DETECT

0

1

1

1

SERIAL DATA OUTPUT

100

0

RESERVED

100

1

RESERVED

1

0

1

0

CLK DIVIDER OUTPUT

101

1

RESERVED

1

1

0

0

FAST-LOCK SWITCH

110

1

R-DIVIDER/2

111

0

N-DIVIDER/2

1

1

1

1

READBACK TO MUXOUT

R1 RAMP ON

0

RAMP DISABLED

RAMP ENABLED

1

F25

F24

..........

F15

F14

MSB FRACTIONAL VALUE

(FRAC)*

0

0

..........

0

0

0

0

0

..........

0

1

1

0

0

..........

1

0

2

0

0

..........

1

1

3

.

.

..........

.

.

.

.

.

..........

.

.

.

.

.

..........

.

.

.

1

1

..........

0

0

4092

1

1

..........

0

1

4093

1

1

..........

1

0

4094

1

1

..........

1

1

4095

N12

N11

N10

N9N8N7N6

N5N4

N3N2N1

INTEGER VALUE

(INT)

0

0

0

000

01

0

111

23

0

0

0

000

01

1

000

24

0

0

0

000

01

1

001

25

0

0

0

000

01

1

010

26

.

.

.

...

...

...

.

.

.

.

...

...

...

.

.

.

.

...

...

...

.

1

1

1

111

11

1

101

4093

1

1

1

111

11

1

110

4094

1

1

1

111

11

1

111

4095

*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN

REGISTER R0, AND THE 13-BIT LSB REGISTER STORED IN

Figure 22. FRAC/INT Register (R0) Map