ADF4158 datasheet(30/36 Pages) AD

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ADF4158

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CLK

MUXOUT

TXDATA

DATA

R0 WRITE

R4 WRITE

FREQUENCY

READBACK

FREQUENCY

READBACK

FREQUENCY

READBACK

37 CLK

PULSES

37 CLK

PULSES

37 CLK

PULSES

32 CLK

PULSES

32 CLK

PULSES

32 CLK

PULSES

Figure 42. Continuous Frequency Readback

For continuous frequency readback the following sequence

should be used:

•

LE high

•

Pulse on TXDATA

•

Frequency readback (as described at the beginning of the

Interrupt Modes and Frequency Readback section and

Figure 41)

•

Pulse on TXDATA

•

Frequency readback (as described at the beginning of the

Interrupt Modes and Frequency Readback section and

Figure 41)

•

Pulse on TXDATA

•

…

The sequence is also shown in Figure 42.

FAST-LOCK TIMER AND REGISTER SEQUENCES

If the fast-lock mode is used, a timer value needs to be

loaded into the PLL to determine the time spent in wide

bandwidth mode.

When the DB[20:19] bits in Register 4 (R4) are set to 01 (fast-

lock divider), the timer value is loaded via the 12-bit clock

divider value. To use fast lock, the PLL must be written to in

the following sequence:

Initialization sequence (see the Initialization Sequence

section). This should only be performed once after

powering up the part.

Load Register R4 DB[16:15] = 01 and the chosen fast-lock

timer value (DB[18:7]).

Load Register R2 with the chosen MOD divider value

(DB[14:3]) if longer time in wide loop bandwidth is

required.

Note that the duration that the PLL remains in wide bandwidth

is equal to the MOD × fast-lock timer/fPFD, where MOD is the

12-bit MOD divider in Register R2.

In addition, note that the fast-lock feature doesn’t work in

ramp mode.

FAST LOCK: AN EXAMPLE

If a PLL has a reference frequency of 13 MHz, that is, fPFD =

13 MHz, as well as MOD = 10 (12-bit MOD divider in Register

R2) and a required lock time of 50 μs, the PLL is set to wide

bandwidth for 40 μs.

If the time period set for the wide bandwidth is 40 μs, then

Fast-Lock Timer Value = Time in Wide Bandwidth × fPFD/MOD

Fast-Lock Timer Value = 40 μs × 13 MHz /10 = 52.

Therefore, 52 must be loaded into the clock divider value in

Timer and Register Sequences section.

FAST LOCK: LOOP FILTER TOPOLOGY

To use fast-lock mode, an extra connection from the PLL to the

loop filter is needed. The damping resistor in the loop filter

must be reduced to ¼ of its value while in wide bandwidth

mode. This is required because the charge pump current is

increased by 16 while in wide bandwidth mode, and stability

must be ensured. To further enhance stability and mitigate

frequency overshoot while frequency change (in wide band-

width mode), Register R3 is connected. During fast lock, the

SW1 pin is shorted to ground and SW2 is connected to CP (it

is done by setting Bits DB[20:19] in Register R4 to 01—fast lock

divider). The following two topologies can be used:

•

Divide the damping resistor (R1) into two values (R1 and

R1A) that have a ratio of 1:3 (see Figure 43).

•

Connect an extra resistor (R1A) directly from SW1, as shown

in Figure 44. The extra resistor must be chosen such that

the parallel combination of an extra resistor and the damping

resistor (R1) is reduced to ¼ of the original value of R1.

For both of the topologies, the ratio R3:R2 should equal 1:4.

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