ADF4158 datasheet(18/36 Pages) AD

18 / 36 page

ADF4158

Rev. 0 | Page 18 of 36

FUNCTION REGISTER (R3) MAP

With Register R3 DB[2:0] set to [0, 1, 1], the on-chip function

Reserved Bits

All reserved bits should be set to 0 for normal operation.

N SEL

This setting is used to circumvent the issue of pipeline delay

between an update of the integer and fractional values in the

N-counter. Typically, the INT value is loaded first, followed by

the FRAC value. This can cause the N-counter value to be at an

incorrect value for a brief period of time equal to the pipeline

delay (about four PFD cycles). This has no effect if the INT

value has not been updated. However, if the INT value has been

changed, this can cause the PLL to overshoot in frequency while

it tries to lock to the temporarily incorrect N value. After the

correct fractional value is loaded, the PLL quickly locks to the

correct frequency. Introducing an additional delay to the load-

ing of the INT value using the N SEL bit causes the INT and

FRAC values to be loaded at the same time, preventing frequency

overshoot. The delay is turned on by setting Bit DB15 to 1.

SD Reset

For most applications, DB14 should be set to 0. When DB14 is

set to 0, the Σ-Δ modulator is reset on each write to Register R0.

If it is not required that the Σ-Δ modulator be reset on each

Ramp Mode

DB[11:10] determine the type of generated waveform.

PSK Enable

When DB9 is set to 1, PSK modulation is enabled. When set to

0, PSK modulation is disabled.

FSK Enable

When DB8 is set to 1, FSK modulation is enabled. When set to

0, FSK modulation is disabled.

Lock Detect Precision (LDP)

When DB7 is programmed to 0, 24 consecutive PFD cycles of

15 ns must occur before digital lock detect is set. When this bit

is programmed to 1, 40 consecutive reference cycles of 15 ns

must occur before digital lock detect is set.

Phase Detector (PD) Polarity

DB6 sets the phase detector polarity. When the VCO

characteristics are positive, set this bit to 1. When the

VCO characteristics are negative, set this bit to 0.

Power-Down

DB5 provides the programmable power-down mode. Setting

this bit to 1 performs a power-down. Setting this bit to 0 returns

the synthesizer to normal operation. While in software power-

down mode, the part retains all information in its registers.

Only when supplies are removed are the register contents lost.

When a power-down is activated, the following events occur:

All active dc current paths are removed.

The synthesizer counters are forced to their load state

conditions.

The charge pump is forced into three-state mode.

The digital lock-detect circuitry is reset.

The RFIN input is debiased.

The input register remains active and capable of loading

and latching data.

Charge Pump Three-State

DB4 puts the charge pump into three-state mode when

programmed to 1. It should be set to 0 for normal operation.

Counter Reset

DB3 is the RF counter reset bit. When this bit is set to 1, the RF

synthesizer counters are held in reset. For normal operation, set

this bit to 0.

ADF4158 Datasheet(PDF) 18 Page - Analog Devices

ADF4158 Datasheet(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL