ADF4158

Rev. 0 | Page 21 of 36

DEVIATION REGISTER (R5) MAP

With Register R5 DB[2:0] set to [1, 0, 1], the on-chip deviation

register is programmed as shown in Figure 27.

Reserved Bits

All reserved bits should be set to 0 for normal operation.

Tx Ramp CLK

Setting DB29 to 0 uses the clock divider clock for clocking the

ramp. Setting DB29 to 1 uses the Tx data clock for clocking

the ramp.

PAR Ramp

Setting DB28 to 1 enables the parabolic ramp. Setting DB28 to 0

disables the parabolic ramp.

Interrupt

DB[27:26] determine which type of interrupt is used. This

feature is used for reading back the INT and FARC value of a

pin triggers the interrupt). From these bits, frequency can be

obtained. After readback, the sweep might continue or stop

at the readback frequency.

FSK Ramp Enable

Setting DB25 to 1 enables the FSK ramp. Setting DB25 to 0

disables the FSK ramp.

Ramp 2 Enable

Setting DB24 to 1 enables the second ramp. Setting DB24 to 0

disables the second ramp.

Deviation Select

Setting DB23 to 0 chooses the first deviation word. Setting

DB23 to 1, chooses the second deviation word.

4-Bit Deviation Offset Word

DB[22:19] determine the deviation offset. The deviation offset

affects the deviation resolution.

16-Bit Deviation Word

DB[18:3] determine the signed deviation word. The deviation

word defines the deviation step.

DB31

16-BIT DEVIATION WORD

CONTROL

BITS

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

TR1

PR1

I2

I1

FRE1 R2E1 DS1

DO4 DO3 DO2 DO1

D16

D15 D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

C3(1) C2(0) C1(1)

I2

I1

INTERRUPT

0

0

INTERRUPT OFF

11

LOAD CHANNEL CONTINUE SWEEP

D16

D14

.......... D2

D1

16-BIT DEVIATION WORD

0

0

..........

0

0

0

0

0

..........

0

1

1

0

0

..........

1

0

2

0

0

..........

1

1

3

1

1

..........

1

1

–1

1

1

..........

1

0

–2

1

1

..........

0

1

–3

1

0

..........

0

0

–32,768

D4

D3

D1

D2

4-BIT DEV OFFSET

WORD

PR1

PAR RAMP

0DISABLED

1

ENABLED

0

1

0

1

NOT USED

LOAD CHANNEL STOP SWEEP

FRE1 FSK RAMP ENABLE

0DISABLED

1

ENABLED

R2E1

RAMP 2 ENABLE

0

DISABLED

1

ENABLED

DO4

DO3

DO2

DO1

4-BIT DEV OFFSET WORD

00

0

0

0

00

0

1

1

00

1

0

2

00

1

1

3

....

....

....

11

0

1

13

11

1

0

14

11

1

1

15

DS1

DEV SEL

0

DEV WORD 1

1

DEV WORD 2

TR1 TX RAMP CLK

0CLK DIV

1

TX DATA

0

1

..........

1

1

32,767

.

.

..........

.

.

.

.

.

..........

.

.

.

Figure 27. Deviation Register (R5) Map