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HAL810 Datasheet(PDF) 25 Page - Micronas |
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HAL810 Datasheet(HTML) 25 Page - Micronas |
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25 / 30 page ![]() DATA SHEET HAL810 Micronas Feb. 6, 2009; DSH000034_003EN 25 5. Programming of the Sensor 5.1. Definition of Programming Pulses The sensor is addressed by modulating a serial tele- gram on the supply voltage. The sensor answers with a serial telegram on the output pin. The bits in the serial telegram have a different bit time for the VDD-line and the output. The bit time for the VDD-line is defined through the length of the Sync Bit at the beginning of each telegram. The bit time for the output is defined through the Acknowledge Bit. A logical “0” is coded as no voltage change within the bit time. A logical “1” is coded as a voltage change between 50% and 80% of the bit time. After each bit, a voltage change occurs. 5.2. Definition of the Telegram Each telegram starts with the Sync Bit (logical 0), 3 bits for the Command (COM), the Command Parity Bit (CP), 4 bits for the Address (ADR), and the Address Parity Bit (AP). There are different telegram formats: – Write a register (see Fig. 5–2) After the AP Bit, follow 14 Data Bits (DAT) and the Data Parity Bit (DP). If the telegram is valid and the command has been processed, the sensor answers with an Acknowledge Bit (logical 0) on the output. – Read a register (see Fig. 5–3) After evaluating this command, the sensor answers with the Acknowledge Bit, 14 Data Bits, and the Data Parity Bit on the output. – Programming the EEPROM cells (see Fig. 5–4) After evaluating this command, the sensor answers with the Acknowledge Bit. After the delay time tw, the supply voltage rises up to the programming volt- age. Fig. 5–1: Definition of logical 0 and 1 bit tr tf tp0 tp0 logical 0 VDDH VDDL or tp0 logical 1 VDDH VDDL or tp0 tp1 tp1 Table 5–1: Telegram parameters Symbol Parameter Pin Min. Typ. Max. Unit Remarks VDDL Supply Voltage for Low Level during Programming 15 5.6 6 V VDDH Supply Voltage for High Level during Programming 1 6.8 8.0 8.5 V tr Rise Time 1 −− 0.05 ms tf Fall Time 1 −− 0.05 ms tp0 Bit Time on VDD 1 1.7 1.75 1.8 ms tp0 is defined through the Sync Bit tpOUT Bit Time on Output Pin 3 2 3 4 ms tpOUT is defined through the Acknowledge Bit tp1 Voltage Change for Logical 1 1, 3 50 65 80 % % of tp0 or tpOUT VDDPROG Supply Voltage for Programming the EEPROM 1 12.4 12.5 12.6 V tPROG Programming Time for EEPROM 1 95 100 105 ms trp Rise Time of Programming Voltage 1 0.2 0.5 1 ms tfp Fall Time of Programming Voltage 1 0 − 1ms tw Delay Time of Programming Voltage after Acknowledge 10.5 0.7 1 ms |
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