AD9265 datasheet(35/44 Pages) AD

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AD9265

Rev. A | Page 35 of 44

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers,

the SDIO/DCS pin and the SCLK/DFS pin serve as standalone

CMOS-compatible control pins. When the device is powered

up, it is assumed that the user intends to use the pins as static

control lines for the duty cycle stabilizer and output data format

feature control. In this mode, connect the CSB chip select to

AVDD, which disables the serial port interface.

The OEB pin, the DITHER pin, the LVDS pin, the LVDS_RS

pin, and the PDWN pin are active control lines in both external

pin mode and SPI mode. The input from these pins or the SPI

the part.

Table 15. Mode Selection

External

Voltage

Configuration

SDIO/DCS

SVDD (default)

Duty cycle stabilizer enabled

AGND

Duty cycle stabilizer disabled

SCLK/DFS

SVDD

Twos complement enabled

AGND (default)

Offset binary enabled

OEB

DRVDD

Outputs in high impedance

AGND (default)

Outputs enabled

PDWN

AVDD

Chip in power-down or standby

mode

AGND (default)

Normal operation

LVDS

AGND (default)

CMOS output mode

AVDD

LVDS output mode

LVDS_RS

AGND (default)

ANSI LVDS output levels

AVDD

Reduced swing LVDS output

levels

DITHER

AGND (default)

Dither disabled

AVDD

Dither enabled

SPI ACCESSIBLE FEATURES

Table 16 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in AN-877 Application Note, Interfacing to High Speed ADCs via

SPI. The AD9265 part-specific features are described in detail

following Table 17, the external memory map register table.

Table 16. Features Accessible Using the SPI

Feature

Name

Description

Mode

Allows the user to set either power-down mode or

standby mode

Clock

Allows the user to access the DCS, set the clock

divider, set the clock divider phase, and enable

the SYNC input

Offset

Allows the user to digitally adjust the converter

offset

Test I/O

Allows the user to set test modes to have known

data on output bits

Output Mode

Allows the user to set the output mode

Output Phase

Allows the user to set the output clock polarity

Output Delay

Allows the user to vary the DCO delay

VREF

Allows the user to set the reference voltage

DON’T CARE

SDIO

SCLK

CSB

tDH

tCLK

tDS

R/W

A12

A11

A10

tLOW

tHIGH

Figure 84. Serial Port Interface Timing Diagram

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