AD9265 datasheet(13/44 Pages) AD

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AD9265

Rev. A | Page 13 of 44

SYNC

CLK+

CLK–

AVDD

OEB

DCO–

DCO+

D0/1–

D0/1+

D2/3–

D2/3+

DITHER

AVDD

SVDD

CSB

SCLK/DFS

SDIO/DCS

DRVDD

OR+

OR–

D14/15+

D14/15–

AVDD

AD9265

INTERLEAVED

LVDS

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

NOTES

1. DNC = DO NOT CONNECT.

2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE

PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD

MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.

Figure 5. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)

Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

13, 20, 29

DRVDD

Supply

Digital Output Driver Supply (1.8 V Nominal).

4, 5, 34, 36, 45

AVDD

Supply

Analog Power Supply (1.8 V Nominal).

SVDD

Supply

SPI Input/Output Voltage.

39, 40

DNC

Do Not Connect.

AGND

Ground

Analog Ground. The exposed thermal pad on the bottom of the package provides the

analog ground for the input. This exposed pad must be connected to ground for proper

operation.

ADC Analog

VIN+

Input

Differential Analog Input Pin (+).

VIN−

Input

Differential Analog Input Pin (−).

VREF

Input/output

Voltage Reference Input/Output.

SENSE

Input

Voltage Reference Mode Select. See Table 11 for details.

RBIAS

Input/output

External Reference Bias Resistor.

VCM

Output

Common-Mode Level Bias Output for Analog Inputs.

CLK+

Input

ADC Clock Input—True.

CLK−

Input

ADC Clock Input—Complement.

Digital Input

SYNC

Input

Digital Synchronization Pin. Slave mode only.

Digital Outputs

D0/1+

Output

LVDS Output Data Bit 0/Bit 1 (LSB)—True.

D0/1−

Output

LVDS Output Data Bit 0/Bit 1 (LSB)—Complement.

D2/3+

Output

LVDS Output Data Bit 2/Bit 3—True.

D2/3−

Output

LVDS Output Data Bit 2/Bit 3—Complement.

D4/5+

Output

LVDS Output Data Bit 4/Bit 5—True.

D4/5−

Output

LVDS Output Data Bit 4/Bit 5—Complement.

D6/7+

Output

LVDS Output Data Bit 6/Bit 7—True.

D6/7−

Output

LVDS Output Data Bit 6/Bit 7—Complement.

D8/9+

Output

LVDS Output Data Bit 8/Bit 9 —True.

D8/9−

Output

LVDS Output Data Bit 8/Bit 9—Complement.

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