| Electronic Components Datasheet Search |
|
HCS12 Datasheet(PDF) 220 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
HCS12 Datasheet(HTML) 220 Page - Freescale Semiconductor, Inc |
|
220 / 452 page ![]() Instruction Glossary S12CPUV2 Reference Manual, Rev. 4.0 220 Freescale Semiconductor Operation: Effective Address ⇒ SP Description: Loads the stack pointer with an effective address specified by the program. The effective address can be any indexed addressing mode operand address except an indirect address. Indexed addressing mode operand addresses are formed by adding an optional constant supplied by the program or an accumulator value to the current value in X, Y, SP, or PC. See 3.9 Indexed Addressing Modes for more details. LEAS does not alter condition code bits. This allows stack modification without disturbing CCR bits changed by recent arithmetic operations. Operation is a bit more complex when LEAS is used with auto-increment or auto-decrement operand specifications and the SP is the referenced index register. The index register is loaded with what would have gone out to the address bus in the case of a load index instruction. In the case of a pre-increment or pre-decrement, the modification is made before the index register is loaded. In the case of a post-increment or post-decrement, modification would have taken effect after the address went out on the address bus, so post-modification does not affect the content of the index register. In the unusual case where LEAS involves two different index registers and post-increment or post-decrement, both index registers are modified as demonstrated by the following example. Consider the instruction LEAS 4,Y+. First S is loaded with the value of Y, then Y is incremented by 4. LEAS Load Stack Pointer with Effective Address LEAS CCR Details: S X HIN Z V C –––––––– Source Form Address Mode Object Code Access Detail HCS12 M68HC12 LEAS oprx0_xysp LEAS oprx9,xysp LEAS oprx16,xysp IDX IDX1 IDX2 1B xb 1B xb ff 1B xb ee ff Pf PO PP PP (1) PO PP 1. Due to internal M68HC12 CPU requirements, the program word fetch is performed twice to the same address during this instruction. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |