HCS12 datasheet(52/452 Pages) FREESCALE

52 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

4.4.3.1 Short Branches

The “not-taken” case for short branches is simple. Since the instruction

consists of a single word containing both an opcode and an 8-bit offset, the

queue advances, another program word is fetched, and execution continues

with the next instruction.

The “taken” case for short branches requires that the queue be refilled so

that execution can continue at a new address. First, the effective address of

the destination is calculated using the relative offset in the instruction. Then,

the address is loaded into the program counter, and the CPU performs three

program word fetches at the new address to refill the instruction queue.

4.4.3.2 Long Branches

The “not-taken” case for all long branches requires three cycles, while the

“taken” case requires four cycles. This is due to differences in the amount of

program information needed to fill the queue.

Long branch instructions begin with a $18 prebyte which indicates that the

opcode is on page 2 of the opcode map. The CPU12 treats the prebyte as

a special one-byte instruction. If the prebyte is not aligned, the first cycle is

used to perform a program word access; if the prebyte is aligned, the first

cycle is used to perform a free cycle. The first cycle for the prebyte is

executed whether or not the branch is taken.

The first cycle of the branch instruction is an optional cycle. Optional cycles

make the effects of byte-sized and misaligned instructions consistent with

those of aligned word-length instructions. Program information is always

fetched as aligned 16-bit words. When an instruction has an odd number of

bytes, and the first byte is not aligned with an even byte boundary, the

optional cycle makes an additional program word access that maintains

queue order. In all other cases, the optional cycle is a free cycle.

In the “not-taken” case, the queue must advance so that execution can

continue with the next instruction. Two cycles are used to refill the queue.

Alignment determines how the second of these cycles is used.

In the “taken” case, the effective address of the branch is calculated using

the 16-bit relative offset contained in the second word of the instruction. This

address is loaded into the program counter, then the CPU performs three

program word fetches at the new address.

HCS12 Datasheet(PDF) 52 Page - Freescale Semiconductor, Inc