HCS12 datasheet(23/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

loads the program counter with the previously stacked return address and

execution continues at that address.

When an interrupt occurs, the current instruction finishes execution. The

address of the next instruction is calculated and pushed onto the stack, all

the CPU registers are pushed onto the stack, the program counter is loaded

with the address pointed to by the interrupt vector, and execution continues

at that address. The stacked registers are referred to as an interrupt stack

frame. The CPU12 stack frame is the same as that of the M68HC11.

NOTE:

These instructions can be interrupted, and they resume execution once the

interrupt has been serviced:

• REV (fuzzy logic rule evaluation)

• REVW (fuzzy logic rule evaluation (weighted))

• WAV (weighted average)

2.2.4 Program Counter

The program counter (PC) is a 16-bit register that holds the address of the

next instruction to be executed. It is automatically incremented each time an

instruction is fetched.

2.2.5 Condition Code Register

The condition code register (CCR), named for its five status indicators,

contains:

• Five status indicators

• Two interrupt masking bits

• STOP instruction control bit

HCS12 Datasheet(PDF) 23 Page - Freescale Semiconductor, Inc